MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 284

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

System Integration Module (SIM60)
6.9.3.10 PLL CONTROL REGISTER (PLLCR). The PLLCR controls the operation of the
PLL. It can be read or written only in supervisor mode. Writing into this register is allowed
only if the PLLWP bit is zero. The reset state of PLLCR produces an operating frequency of
13.14 MHz when the PLL is referenced to a 32.768-kHz crystal or to 4.192 MHz. Two pins
(MODCK1–MODCK0) are sampled during hardware reset (see Table 6-1).
Note:
6-40
RESET:
PLLEN
The default value is one unless MODCK1-MODCK0 pins are tdriven with 00 during reset.
15
without generating spikes on the CLKO1 pin. If the CLKO1 pin is not connected to external
circuits, set both bits (disabling the clock output) to minimize noise and power dissipation.
The COM1 bits are cleared at system reset, unless MODCK = 01, in which case they are
ones. This prevents CLKO1 and CLKO2 from both defaulting to an active state after reset,
for all four combinations of the MODCK1-0 pins. This reduces the potential for system
noise at reset. CLKO1 may be enabled later, if desired.
1*
00 = Clock Out Enabled, Full-Strength Output Buffer
01 = Clock Out Enabled, 2/3-Strength Output Buffer
10 = Clock Out Enabled, 1/3-Strength Output Buffer
11 = Clock Out Disabled (Driving 1).
PLLWP PREEN
14
0
If a continuous clock source is needed by the user when MOD-
CK = 01, then the user should use the output of the external os-
cillator instead of the CLKO1 pin.
The sum of strength of CLKO1 and CLKO2 should not exceed
1. (If COM2 is set to 2/3 drive configuration, then COM1 cannot
be greater than 1/3 drive configuration)
When MODCK is set to 01, CLOCKO1 is disabled at reset until
the COM1 bit is changed.
The CLKO1 logic is as follows:
when COM1 bits in the CLKOCR = 11, CLKO1 is driven high;
13
0
when COM1 bits in the CLKOCR 11, CLKO1 is driven accord-
ing to the following conditions:
STSIM
12
0
a. Driven low if the PLL is NOT locked AND RESETH is
b. Driven with the same frequency as EXTAL clock if the
c. Driven low if the PLL unlocked due to MF change.
asserted.
PLL is locked.
MF11
11
Freescale Semiconductor, Inc.
0
For More Information On This Product,
MF10
10
0
MC68360 USER’S MANUAL
Go to: www.freescale.com
MF9
9
0
MODCK1 MODCK1
MF8
8
NOTE
MF7
7
MF6
6
0
MF5
5
0
MODCK1
MF4
4
MF3
0
3
MF2
2
0
MF1
1
0
MF0
0
0