MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 448

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
Serial Communication Controllers (SCCs)
ready; thus, the CP will not use a BD twice until the BD has been confirmed by the CPU32+
core. (The one exception to this rule is that the QUICC supports an option for repeated trans-
mission, called the continuous mode, whereby the R-bit is left in the ready position. This is
available in some protocols.)
The CP uses the Rx BDs in a similar fashion. Once the receive side of an SCC is enabled,
it starts with the first BD in that SCC’s Rx BD table. Once data arrives from the serial line
into the SCC, the CP performs certain required protocol processing on the data and moves
the resultant data to the data buffer pointed to by the first BD. Use of a BD is complete when
there is no more room left in the buffer or when certain events occur, such as detection of
an error or an end-of-frame. Whatever the reason, the buffer is then said to be closed, and
additional data will be stored using the next BD. Whenever the CP needs to begin using a
BD because new data is arriving, it will check the E-bit of that BD. If the current BD is not
empty, it will report a busy error. However, it will not move from the current BD until it
becomes empty. When the CP sees the W-bit set in a BD, it goes back to the beginning of
the BD table after processing of the BD is complete. After using a BD, the CP sets the E-bit
to not-empty; thus, the CP will never use a BD twice until the BD has been processed by the
CPU32+ core. (The one exception to this rule is that the QUICC supports an option for
repeated reception, called the continuous mode, whereby the E-bit is left in the empty posi-
tion. This is available in some protocols.)
7.10.7 SCC Parameter RAM
Each SCC parameter RAM area begins at the same offset from each SCC base area. The
protocol-specific portions of the SCC parameter RAM are discussed in the specific protocol
descriptions. The part of the SCC parameter RAM that is the same for all SCC protocols is
shown in Table 7-5.
Certain parameter RAM values (marked in boldface) need to be initialized by the user before
the SCC is enabled; other values are initialized/written by the CP. Once initialized, most
parameter RAM values will not need to be accessed in user software since most of the activ-
ity is centered around the transmit and Rx BDs, not the parameter RAM. However, if the
parameter RAM is accessed by the user, the following regulations should be noted. The
parameter RAM can be read at any time. The parameter time values related to the SCC
transmitter can only be written whenever the transmitter is disabled (see 7.10.14 Disabling
the SCCs on the Fly), after a STOP TRANSMIT and before a RESTART TRANSMIT com-
mand, or after the buffer/frame completes transmission as a result of a GRACEFUL STOP
TRANSMIT command and before a RESTART TRANSMIT command. The parameter RAM
values related to the SCC receiver can only be written when the receiver is disabled (see
7.10.14 Disabling the SCCs on the Fly).
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MC68360 USER’S MANUAL
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