MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 485

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

E—Empty
Bits 14, 6, 2—Reserved
W—Wrap (Final BD in Table)
I—Interrupt
C—Control Character
A—Address
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
NOTE: Entries in boldface must be initialized by the user.
0 = The data buffer associated with this Rx BD has been filled with received data, or
1 = The data buffer associated with this BD is empty, or reception is currently in
0 = This is not the last BD in the Rx BD table.
1 = This is the last BD in the Rx BD table. After this buffer has been used, the CP will
0 = No interrupt is generated after this buffer has been filled.
1 = The RX bit in the UART event register will be set when this buffer has been com-
0 = This buffer does not contain a control character.
1 = This buffer contains a control character. The last byte in the buffer is one of the
0 = The buffer contains data only.
1 = When working in non-automatic multidrop mode, this bit indicates that the first byte
data reception has been aborted due to an error condition. The CPU32+ core is
free to examine or write to any fields of this Rx BD. The CP will not use this BD
again while the E-bit remains zero.
progress. This Rx BD and its associated receive buffer are owned by the CP. Once
the E-bit is set, the CPU32+ core should not write any fields of this Rx BD.
receive incoming data into the first BD in the table (the BD pointed to by RBASE).
The number of Rx BD s in this table is programmable and is determined only by
the W-bit and the overall space constraints of the dual-port RAM.
pletely filled by the CP, indicating the need for the CPU32+ core to process the
buffer. The RX bit can cause an interrupt if it is enabled.
user-defined control characters.
of this buffer contains an address byte. The address comparison should be imple-
mented in software. In automatic multidrop mode, this bit indicates that the BD con-
tains a message received immediately after an address recognized in UADDR1 or
UADDR2. This address is not written into the receive buffer.
15
E
14
—
13
Freescale Semiconductor, Inc.
W
For More Information On This Product,
12
I
MC68360 USER’S MANUAL
Go to: www.freescale.com
11
C
10
A
CM
RX DATA BUFFER POINTER
9
DATA LENGTH
ID
8
AM
Serial Communication Controllers (SCCs)
7
—
6
BR
5
FR
4
PR
3
—
2
OV
1
CD
0