MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 301

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

provide one additional wait state for external masters, giving up to 15 wait states by the chip
selects. This is programmed using the TCYC bits in the OR.
6.11.5 Address and Address Space Checking
The defined base address is written to the BR. The address mask bits for that address are
written to the OR. The function code access value, if desired, is written to FC bits in the BR.
The FCM bits in the OR may be used to mask this selection. If the address space (function
code) checking is not desired, program the FCM bits to zero. Also, the chip select can be
configured not to assert during CPU space (i.e., interrupt acknowledge) cycles that have a
function code value 0111. This option is decided with the NCS bit in the GMR.
6.11.6 SRAM Bank Parity
Parity can be configured for any SRAM bank. Parity is generated and checked on a per-byte
basis using PRTY3–PRTY0 if the PAREN bit is set in the BR. The OPAR bit in the GMR
determines the type of parity (odd or even), and the PBEE bit in the GMR determines if an
internal master should generate an error as a result of a parity error. Any parity error acti-
vates the PERR pin until the associated PERx bit in the MSTAT is cleared.
6.11.7 External Master Support
The SRAM banks support the internal bus masters, such as the CPU32+, IDMAs, and
SDMAs, as well as external bus masters, such as the QUICC, MC68030, or MC68EC040.
In the case of an external master, an additional wait state may be programmed into the
SRAM bank to compensate for the additional decoding time. This capability is programmed
in the EMWS bit of the GMR.
The MC68EC040 must always be synchronous to the QUICC clock. The SRAM bank sup-
ports bursting by the MC68EC040 if the BACK40 bit in the BR is set. During this access, CS,
PRTYx, PERR, DSACK/TA/TBI, and BADDR3–BADDR2 are all valid signals. The SRAM
bank waits for the MC68EC040 TS line to be asserted before starting any MC68EC040
access. Burst (line fill) transfers are also supported.
The chip-select logic supports MC68030/QUICC external masters in two modes. In the
asynchronous mode, the logic asserts the CS and DSACK lines as soon as an address
match is detected from the external master. The chip select in this mode is waiting for the
external master’s AS line to be asserted. In the synchronous mode, the CS and DSACK
assertion and negation timings are synchronous. The synchronous mode is programmed in
the SYNC bit of the GMR.
Asynchronous external masters do not have parity support.
DW40 bit in the GMR must be set to support parity with external
040 master.
Parity is not supported for bus cycles terminated with external
assertion of DSACK or TA.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
System Integration Module (SIM60)