MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 437
MC68EN360AI25VL
Manufacturer Part Number
MC68EN360AI25VL
Description
Manufacturer
Freescale
Datasheet
1.MC68EN360AI25VL.pdf
(962 pages)
Specifications of MC68EN360AI25VL
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Lead Free Status / RoHS Status
Compliant
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TTX—Transparent Transmitter
CDP—CD Pulse
CTSP—CTS Pulse
The QUICC SCCs offer totally transparent operation. However, to increase flexibility, to-
tally transparent operation is not configured with the MODE bits, but with the TTX and
TRX bits. This gives the user the opportunity to implement unique applications, such as
an SCC receiver configured to HDLC and the transmitter configured to totally transparent
operation. To do this, set MODE = HDLC, TTX = 1, and TRX = 0.
This mode is similar to the way the CD (sync) pin is used on the MC68302 in totally trans-
parent mode. To mimic this behavior on the QUICC, the external sync signal should be
connected to the CD and CTS pins on the QUICC, and the CDP and CTSP bits should be
set.
0 = Normal operation.
1 = The transmitter operates in totally transparent mode, regardless of the protocol se-
0 = Normal operation—envelope mode. The CD pin should envelope the frame, and
1 = Pulse mode. Once the CD pin is asserted, synchronization has been achieved, and
0 = Normal operation—envelope mode. The CTS pin should envelope the frame, and
1 = Pulse mode. Once the CTS pin is asserted, synchronization has been achieved,
lected for the receiver in the MODE bits.
negating CD while receiving will cause a CD lost error.
further transitions of CD will have no effect on reception.
a negation of CTS while transmitting will cause a CTS lost error.
and further transitions of CTS will have no effect on transmission.
Full-duplex totally transparent operation for an SCC is obtained
by setting both TTX and TRX.
An SCC cannot operate with Ethernet on its transmitter simulta-
neously with transparent operation on its receiver, or erratic be-
havior will result. In other words, if the GSMR MODE = Ethernet,
TTX must equal TRX, or erratic operation will result.
Full-duplex totally transparent operation for an SCC is obtained
by setting both TTX and TRX.
An SCC cannot operate with Ethernet on its receiver simulta-
neously with transparent operation on its transmitter, or erratic
behavior will result. In other words, if the GSMR MODE = Ether-
net, TTX must equal TRX, or erratic operation will result.
This bit must be set if this SCC is used in TSA.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
NOTE
NOTE
Serial Communication Controllers (SCCs)
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