MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 512

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Serial Communication Controllers (SCCs)
7-188
5. Connect the CLK7 pin to SCC4 using the SI. Write the R4CS bits in SICR to 110.
6. Connect the SCC4 to the NMSI (i.e., its own set of pins). Clear the SC4 bit
7. Write $0740 to the SDCR to initialize the SDMA Configuration Register.
8. Write RBASE and TBASE in the SCC parameter RAM to point to the Rx BD and Tx
9. Program the CR to execute the INIT RX & TX PARAMS command for this channel."
10. Write RFCR with $18 and TFCR with $18 for normal operation.
11. Write MRBLR with the maximum number of bytes per receive buffer. For this case,
12. Write C_MASK with $0000F0B8 to comply with 16-bit CCITT-CRC.
13. Write C_PRES with $0000FFFF to comply with 16-bit CCITT-CRC.
14. Clear DISFC, CRCEC, ABTSC, NMARC, and RETRC for the sake of clarity.
15. Write MFLR with $0100 to make the maximum frame size 256 bytes.
16. Write RFTHR with $0001 to allow interrupts after each frame.
17. Write HMASK with $0000 to allow all addresses to be recognized.
18. Clear HADDR1, HADDR2, HADDR3, and HADDR4 for clarity.
19. Initialize the Rx BD. Assume the Rx data buffer is at $00001000 in main memory.
20. Initialize the Tx BD. Assume the Tx data frame is at $00002000 in main memory
21. Write $FFFF to the SCCE to clear any previous events.
22. Write $001A to the SCCM to enable the TXE, RXF, and TXB interrupts.
23. Write $08000000 to the CIMR to allow SCC4 to generate a system interrupt. (The
24. Write $00000000 to GSMR_H4 to enable normal behavior of the CTS and CD pins
25. Write $00000000 to GSMR_L4 to configure the CTS and CD pins to automatically
Write the T4CS bits in SICR to 110.
in the SICR.
BDs in the dual-port RAM. Assuming one Rx BD at the beginning of dual-port RAM
and one Tx BD following that Rx BD, write RBASE with $0000 and TBASE with
$0008.
For instance, to execute this command for SCC1, write $0001 to the CR. This com-
mand causes the RBPTR and TBPTR parameters of the serial channel to be updated
with the new values just programmed into RBASE and TBASE.
assume 256 bytes, so MRBLR = $0100. The value 256 was chosen to allow an
entire receive frame to fit into one receive buffer (see MFLR below).
Write $B000 to Rx_BD_Status. Write $0000 to Rx_BD_Length (not required—done
for instructional purposes only). Write $00001000 to Rx_BD_Pointer.
and contains five 8-bit characters. Write $BC00 to Tx_BD_Status. Write $0005 to
Tx_BD_Length. Write $00002000 to Tx_BD_Pointer.
CICR should also be initialized.)
and idles between frames (as opposed to flags).
control transmission and reception (DIAG bits) and the HDLC mode. Normal
operation of the transmit clock is used (TCI is cleared). Notice that the transmitter
(ENT) and receiver (ENR) have not been enabled. If inverted HDLC operation
Freescale Semiconductor, Inc.
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