MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 516

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Serial Communication Controllers (SCCs)
7.10.18.1 HDLC BUS KEY FEATURES. The HDLC bus controller contains the following
key features:
7.10.18.2 HDLC BUS OPERATION. The following paragraphs detail the operation of the
HDLC bus Controller.
7.10.18.2.1 Accessing the HDLC Bus. HDLC bus ensures an orderly access to the bus
when two or more transmitters attempt to access the bus simultaneously. In such a case,
one transmitter will always be successful in completing its transmission. This procedure
relies upon the use of HDLC flags consisting of the binary pattern 01111110 ($7E) and the
use of the zero bit insertion to prevent flag imitation.
While in the active condition (desiring to transmit), the HDLC bus controller will monitor the
bus through the CTS pin. It counts the number of one bits using the CTS pin, and if a zero
is detected, the internal counter is cleared.
Once 8 consecutive ones have been received, the HDLC bus controller will begin transmis-
sion on the line. While it is transmitting information on the bus, the transmitted data is con-
tinuously compared with the data actually on the bus. The CTS pin is used to sample the
external bus.
Figure 7-56 shows how the CTS pin is used. The CTS sample is taken halfway through the
bit time, using the rising edge of the transmit clock. If the transmitted bit is the same as the
received CTS sample, the HDLC bus controller continues its transmission. If, however, the
received CTS bit is zero, but the transmitted bit was 1, the HDLC controller ceases trans-
mission following that bit and returns to the active condition. Since the HDLC bus uses a
wired-OR scheme, a transmitted zero has priority over a transmitted one.
If the source address is included in the HDLC frame in addition to the destination address,
a predefined priority of nodes will result. In addition, the inclusion of a source address will
allow collisions to be detected no later than the end of the source address.
7-192
• Superset of the HDLC Controller Features
• Automatic HDLC Bus Access
• Automatic Retransmission in Case of a Collision
• May Be Used with the NMSI Mode or a TDM Bus
• Delayed RTS Mode
HDLC bus can be used with many different HDLC-based frame
formats. HDLC bus does not specify the type of HDLC protocol
used.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE