MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 398

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Serial Interface with Time Slot Assigner
CSEL—Channel Select
CNT—Count
BYT—Byte Resolution
LST—Last Entry in the RAM
7-74
This value indicates the number of bits/bytes (according to the BYT bit) that the routing
and strobe select of this entry controls. If CNT = 0000, then 1 bit/byte is chosen; if
CNT = 1111, then 16 bits/bytes are selected.
Whenever the SI RAM is used, this bit must be set in one of the Tx or Rx entries of each
group that is used. Even if all entries of a group are used, this bit must still be set in the
last entry.
000 = The bit/byte group is not supported within the QUICC. The transmit data pin is
001 = The bit/byte group is routed to SCC1.
010 = The bit/byte group is routed to SCC2.
011 = The bit/byte group is routed to SCC3.
100 = The bit/byte group is routed to SCC4.
101 = The bit/byte group is routed to SMC1.
110 = The bit/byte group is routed to SMC2.
111 = The bit/byte group is not supported within the QUICC. This code is also used in
0 = Bit resolution—the CNT value indicates the number of bits in this group.
1 = Byte resolution—the CNT value indicates the number of bytes in this group.
0 = This is not the last entry in this section of the route RAM.
1 = This is the last entry in this RAM. After this entry, the SI will wait for the sync signal
to start the next frame.
three-stated, and the receive data pin is ignored.
SCIT mode as the D channel grant (refer to 7.8.7.2.2 SCIT Programming.)
Each strobe is changed with the corresponding RAM clock and
will be output only if the corresponding parallel I/O is configured
as a dedicated pin.
If a strobe is programmed to be asserted in more than one set of
entries (e.g., the SI Rx route for the TDMa entries and the SI Tx
route for TDMb entries both select the same strobe), then the as-
sertion of the strobe corresponds to the logical OR of all possible
sources. This use of the strobes is not useful for most applica-
tions. It is recommended that a given strobe be selected in only
one set of SI RAM entries.
If a second sync signal is received before the end of a frame (as
defined by the last SI RAM entry), an error occurs. The SI will ter-
minate SI RAM processing, and cease transmitting or receiving
data until a third sync signal is received.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTES
NOTE