MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 382

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

SDMA Channels
The read or write operation may take multiple bus cycles if the memory provides less than
a 32-bit port size. For instance, a 32-bit long-word read from a 16-bit memory will take two
SDMA bus cycles. As long as a higher priority bus master does not require the bus during
an SDMA transfer, the entire operand (32 bits on reads and 8, 16, or 32 bits on writes) will
be transferred in back-to-back bus cycles before the SDMA relinquishes the bus. If a higher
priority bus master requests the bus during an operand transfer, it will be granted the bus at
the end of that SDMA bus cycle. Once the higher priority bus master relinquishes the bus,
the SDMA will reacquire the bus and continue any outstanding bus cycles.
The SDMA can steal cycles with no arbitration overhead when the QUICC is in master mode
(i.e., the CPU32+ is enabled) and the external bus is not currently being held by an external
master (see Figure 7-18). Note that in normal operation, the BR, BG, and BGACK signals
are not affected by the SDMA; however, an indication of the SDMA internal bus request can
be obtained from the BCLRO signal.
The SDMA will assert the BCLRO signal when it requests the bus if this capability is pro-
grammed in the SIM60 module configuration register and port E pin assignment register.
BCLRO can be used to clear an external bus master from the external bus, if desired. For
instance, BCLRO can be connected through logic to the external master’s HALT signal, and
then be negated externally when the external master’s AS signal is negated. BCLRO, as
seen from the QUICC, is negated by the SDMA during its access to memory.
7-58
CONTROLLER
RISC
4 SCCs
CPU32+
CORE
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 7-17. SDMA Data Paths
INTERNAL IMB
CHANNELS
14 SDMA
MC68360 USER’S MANUAL
2 SMCs
Go to: www.freescale.com
SERIAL CHANNEL DATA FLOW
2
DUAL-PORT
INTERNAL
1 SPI
RAM
SIM60
QUICC
1
EXTERNAL
RAM
EXTERNAL
ROM