MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 431

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

RST—Reset BRG
EN—Enable BRG Count
EXTC1–EXTC0—External Clock Source
ATB—Autobaud
CD11–CD0—Clock Divider
This bit performs a software reset of the BRG identical to that of an external reset. A reset
disables the BRG and sets the BRGO output clock. (This can only be seen externally if
the BRGO function is enabled to reach the corresponding port B parallel I/O pin.)
This bit is used to dynamically stop the BRG from counting, which may be useful for low-
power modes.
The EXTC bits select the BRG input clock from the internal BRGCLK or one of three ex-
ternal pins.
When set, this bit selects autobaud operation of the BRG on the corresponding RXDx pin.
The clock divider bits, CD11–CD0, and the prescaler determine the BRG output clock
rate. CD11–CD0 are used to preset a 12-bit counter that is decremented at the prescaler
output rate. The counter is not accessible to the user. When the counter reaches zero, it
is reloaded from the clock divider bits. Thus, a value of $FFF in CD11–CD0 produces the
minimum clock rate (divide by 4096), and a value of $0000 produces the maximum clock
rate (divide by 1).
Even when dividing by an odd number, the counter ensures a 50% duty cycle by asserting
the terminal count once on clock low and next on clock high. The terminal count signals
counter expiration and toggles the clock.
0 = Enable the BRG.
1 = Reset the BRG (software reset).
0 = Stop all clocks to the BRG.
1 = Enable clocks to the BRG.
00 = The BRG input clock comes from the BRGCLK (internal clock generated by the
01 = The BRG input clock comes from the CLK2 pin.
10 = The BRG input clock comes from the CLK6 pin.
11 = Reserved.
0 = Normal operation of the BRG.
1 = When RXDx goes low, the BRG will determine the length of the start bit and syn-
chronize the BRG to the actual baud rate.
clock synthesizer in the SIM60).
This bit must remain clear (0) until the SCC receives 3 Rx clocks,
then the user must set this bit to one in order to obtain the correct
baud rate. When the baud rate is obtained and locked it will be
indicated by setting the AB bit in the UART event register.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Baud Rate Generators (BRGs)