MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 693

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

EXTx— External Request to the RISC
7.14.10.5 PORT C INTERRUPT CONTROL REGISTER (PCINT). PCINT is a 16-bit read-
write register. Each defined bit in the PCINT corresponds to a port C line to determine
whether the corresponding port C line will assert an interrupt request upon a high-to-low
change or any change on the pin. The PCINT is cleared at reset.
Bits 15–12—Reserved.
EDMx—Edge Detect Mode for Line x
7.15 CPM INTERRUPT CONTROLLER (CPIC)
The CPIC is the focal point for all interrupts associated with the CPM. The CPIC accepts and
prioritizes all the internal and external interrupt requests from all functional blocks associ-
ated with the CPM. It is also responsible for generating a vector during the CPU interrupt
acknowledge cycle.
The CPIC contains has the following key features:
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These bits should be written with zeros.
The corresponding port C line (PCx) will assert an interrupt request according to the fol-
lowing:
• Twenty-Eight Interrupt Sources (16 Internal and 12 External)
• Sources May Be Assigned to a Programmable Interrupt Level (1–7)
• Programmable Priority Between SCCs
• Two Priority Schemes for the SCCs
• Programmable Highest Priority Request
• Fully Nested Interrupt Environment
• Unique Vector Number for Each Interrupt Source
0 = PCx is a general-purpose interrupt I/O pin, with the direction controlled in PCDIR.
1 = PCx becomes an external request to the RISC controller instead of being a gener-
0 = Any change on PCx generates an interrupt request.
1 = High-to low change on PCx generates an interrupt request.
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If PCDIR configures this pin as an input, this pin can generate an interrupt to the
CPU32+ core, as controlled by the PCINT bits.
al-purpose interrupt pin. The corresponding PCINT bits control when a request is
generated.
—
13
EXTx should only be set, if the user is instructed to do so, during
the initialization of a Motorola-supplied RAM microcode.
12
EDM11
Freescale Semiconductor, Inc.
11
For More Information On This Product,
EDM10
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
EDM9
9
EDM8
NOTE
8
EDM7
7
EDM6
6
EDM5
5
CPM Interrupt Controller (CPIC)
EDM4
4
EDM3
3
EDM2
2
EDM1
1
EDM0
0