MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 735

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

As a further protection, the user may set the MSB in the clock synthesizer registers, writing
all other bits as zero. This will disable further writes to the clock synthesizer registers, pro-
tecting them from inadvertent accesses by the program during the debugging phases.
Step 8: Initialize System Protection
The next step is to protect the system with the bus monitor, double bus fault monitor, and
software watchdog. The bus monitor and double bus fault monitor should be used during
initial debugging. The software watchdog should be disabled at this time if it will not be used.
Step 9: Clear Entire Dual-Port RAM
After a power-on reset, the internal dual-port RAM comes up in a random state. The user
can avoid many potential problems if the entire dual-port RAM is cleared at this time. This
includes the 1762 bytes of internal system RAM as well as the 768 bytes of parameter RAM.
By clearing the entire dual-port RAM, the user can be sure that no feature is accidentally
invoked just because it was not initialized.
Step 10: Write the PEPAR
The next important action is to configure the rest of the system bus pins by writing to the port
E pin assignment register (PEPAR) in the SIM60. In this register, the user will make a num-
ber of choices about which functions are selected on the system bus (e.g., does the user
want 32 address lines or 28 address lines and 4 write enable lines, etc.).
Step 11: Remap Chip Select 0
Up to this point, CS0 has been running with many wait states and has been mapped to the
entire address space. It is now time to configure CS0 to the proper portion of memory con-
trolled by the EPROM and to reduce the number of wait states. This is accomplished by writ-
ing the global memory register (GMR), option register 0 (OR0), and base register 0 (BR0) in
the memory controller. Note that the valid bit in the BR0 should be set last.
Depending on the details of the application, most GMR bits do not affect CS0, but it is a good
idea to set up GMR before enabling any specific chip select on the QUICC. GMR program-
ming is discussed more fully in 9.1 Minimum System Configuration and 9.4 Using the
QUICC MC68040 Companion Mode.
Step 12: Initialize the System RAM
Ensure that CS0 is programmed correctly—at least for these particular execution
addresses.
It is critical that the user issue a CP reset command to the CR of
the CPM after clearing the entire dual-port RAM. The reset is re-
quired to allow the RISC to reinitialize its internal state variables
for all serial channels, since these variables are stored in the
dual-port RAM and are not necessarily initialized to zeros.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Applications