MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 355

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

The register is incremented using unsigned arithmetic and will roll over if an overflow occurs.
For example, if a register contains $FFFFFFFF and is incremented by one, it will roll over to
$00000000. This register can be incremented by one, two, or four, depending on the SSIZE
bits and the starting address in this register.
The SAPR may be initialized by the host processor or by the RISC controller via a buffer
descriptor's ring structure when the RCI bit is set for special buffer handling modes.
7.6.2.4 DESTINATION ADDRESS POINTER REGISTER (DAPR). The DAPR contains 32
address bits of the destination operand used by the IDMA to access memory or memory-
mapped peripheral controller registers. During the IDMA write cycle, the address on the
master address bus is driven from this register. The DAPR may be programmed by the DAPI
bits to be incremented or remain constant after each operand transfer.
The register is incremented using unsigned arithmetic and will roll over if overflow occurs.
For example, if a register contains $FFFFFFFF and is incremented by one, it will roll over to
$00000000. This register can be incremented by one, two, or four, depending on the DSIZE
bit and the starting address.
The DAPR may be initialized by the host processor or by the RISC controller via a buffer
descriptor's ring structure when the RCI bit is set for special buffer handling modes.
7.6.2.5 FUNCTION CODE REGISTER (FCR). Each IDMA channel has an 8-bit FCR that is
initialized to $00 at reset.
During an IDMA bus cycle, the SFC and DFC bits define the source and destination function
code values that are output by the IDMA and the appropriate address registers. The address
space on the function code lines may be used by an external memory management unit
(MMU) or other memory-protection device to translate the IDMA logical addresses to proper
physical addresses. The function code value programmed into the FCR is placed on pins
FC3–FC0 during a bus cycle to further qualify the address bus value.
7.6.2.6 BYTE COUNT REGISTER (BCR). This 32-bit register specifies the number of bytes
of data to be transferred by the IDMA. The largest value that can be specified is 4 Gbytes
(BCR = $00000000). This register is decremented once for each byte transferred success-
fully, for a total of 1, 2, or 4 per operand transfer. BCR may be even or odd as desired. The
This register is typically set to 1xxx1xxxb to cause the IDMA to
operate in the DMA function code space, as opposed to a CPU
program or data space.
To keep interrupt acknowledge cycles unique in the system, do
not set this register to $77.
Freescale Semiconductor, Inc.
7
For More Information On This Product,
DFC3–DFC0
6
MC68360 USER’S MANUAL
Go to: www.freescale.com
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NOTES
4
3
SFC3–SFC0
2
1
0
IDMA Channels