MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 168

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

CPU32+
5.3.3.10 CONDITION TESTS. Conditional program control instructions and the TRAPcc
instruction execute on the basis of condition tests. A condition test is the evaluation of a log-
ical expression related to the state of the CCR bits. If the result is 1, the condition is true. If
5-26
Instruction
LPSTOP
ILLEGAL
MOVEA
MOVEC
MOVES
TRAPcc
RESET
TRAPV
MOVE
BGND
MOVE
STOP
BKPT
CHK2
TRAP
EORI
EORI
ANDI
ANDI
CHK
RTE
ORI
ORI
# data CCR
# data CCR
# data CCR
# data , SR
# data , SR
# data , SR
CCR, ea
Operand
USP, An
An, USP
ea , CCR
SR, ea
Rn, ea
Syntax
# data
# data
# data
# data
# data
ea , SR
Rc, Rn
Rn, Rc
ea , Dn
ea , Rn
ea , Rn
none
none
none
none
none
none
Table 5-11. System Control Operations
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Operand
Condition Code Register
8, 16, 32
8, 16, 32
16, 32
16, 32
none
none
none
none
none
none
none
none
none
Size
16
16
16
16
32
32
32
32
16
16
16
16
8
8
8
Trap Generating
Privileged
Immediate Data
Immediate Data
Source
SR
USP
An
Rc
Rn
Rn
Source using SFC
Immediate Data V SR
Assert RESET line
(SP)
restore stack according to format
Immediate Data
Immediate Data
If breakpoint cycle acknowledged, then execute re-
turned operation word, else trap as illegal instruction.
If background mode enabled, then enter background
mode, else format/vector offset
PC
If Dn < 0 or Dn < (ea), then CHK exception
If Rn < lower bound or Rn > upper bound, then
CHK exception
SSP – 2
SSP – 4
SSP – 2
llegal instruction vector address
SSP – 2
SSP – 4
vector address
If cc true, then TRAP exception
If V set, then overflow TRAP exception
Immediate Data
Immediate Data
Source
CCR
Immediate Data V CCR
Rn
USP
Rc
Destination using DFC
Destination
– (SSP); SR
SR; SP + 2
An
Destination
SR
CCR
SSP; vector offset
SSP; PC
SSP; SR
SSP; format/vector offset
SSP; PC
PC
SR
CCR
SR
CCR
SR; STOP
SR; interrupt mask
Operation
Rn
– (SSP); (vector)
SP; (SP)
(SSP);
(SSP);
(SSP); SR
SR
SR
SR
CCR
CCR
CCR
(SSP);
– (SSP);
PC; SP + 4
PC
(SSP);
(SSP);
EBI; STOP
PC
SP;