MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 517

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

To ensure that all stations gain an equal share of the bus, a priority mechanism is also imple-
mented in HDLC bus. Once an HDLC bus node has completed the transmission of a frame,
it waits for 10 consecutive one bits, rather than just 8, before beginning the next transmis-
sion. In this way, all nodes desiring to transmit will obtain the bus, before a node transmits
twice. Once a node detects that 10 consecutive ones have occurred on the bus, it may
attempt transmission and can reinstate its original priority of waiting for 8 ones.
7.10.18.2.2 More Performance. Since HDLC bus is used in a wired-OR configuration, the
limit of HDLC bus operation is determined by the rise time of the one bit.
Figure 7-57 shows a method to increase performance. The user supplies a clock that is high
for a shorter duration than it is low, which allows more rise time in the case of a one bit.
(OUTPUT)
(INPUT)
TCLK
TXD
CTS
(OUTPUT)
(INPUT)
TCLK
TXD
CTS
Figure 7-56. HDLC Bus Collision Detection
Figure 7-57. Non-Symmetrical Duty Cycle
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Communication Controllers (SCCs)
CTS SAMPLED AT HALFWAY POINT.
COLLISION DETECTED WHEN
TXD = 1, BUT CTS = 0.
CTS sampled at three quarter point.
Collision detected when
TXD = 1, but CTS = 0.