MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 367

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

pin. Thus, DACKx is the acknowledgment of the original cycle steal request given on the
DREQx pin.
It is possible to cause the IDMA to perform back-to-back cycle steal requests. To achieve
this, DREQx should be asserted to generate the first request, negated, and reasserted dur-
ing the access to the device. If the IDMA detects that DREQx is reasserted prior to the S3
falling edge of the bus cycle to the device (i.e., bus cycle when DACKx is asserted), then
another back-to-back cycle steal request will be performed. Otherwise, the bus is relin-
quished. If DREQx was not reasserted soon enough, a new request will be made to the
IDMA, but the bus will be relinquished and re-requested by the IDMA.
The previous paragraphs discuss the general rules; however, important special cases are
discussed in the following points:
7.6.4.5 IDMA BUS ARBITRATION. Once the IDMA receives a request for a transfer, it
begins arbitrating for the IMB. (The four request types are internal maximum rate, internal
limited rate, external burst, and external cycle steal.)
On the QUICC, the IDMAs, SDMAs, and DRAM refresh controller, called internal masters,
have the capability to become bus master. To determine the relative priority of these mas-
ters, each is given an arbitration ID. The user programs the arbitration ID (a value between
0 and 7) of the IDMAs into the ICCR. The arbitration IDs of the two IDMAs must be different
by a value of 2 (e.g., IDMA1 ID = 2 and IDMA2 ID = 0). These values are used to determine
the relative priority of the IDMA channel and the other internal bus masters.
1. The sample point at the S3 falling edge means the last S3 before the S4 edge that
2. The sample point at S3 assumes that the required setup time is met, as defined in Sec-
3. If SRM is cleared in the CMR (default condition), then DREQx is synchronized inter-
completes the cycle. Thus, if wait states are inserted in the bus cycle, the sample point
is later in the cycle.
tion 10 Electrical Characteristics.
nally before it is used; therefore, DREQx must be reasserted one clock earlier than the
S3 falling edge to be recognized on that cycle and generate a back-to-back request.
To generate back-to-back cycle steal requests, DREQx should
be reasserted after DACKx is asserted, but before the S3 falling
DSACKx pins are also sampled at falling S3 to determine the
end of the bus cycle.
Typically, the IDMA IDs are configured by the user to be the low-
est of the internal bus masters.
edge. Instead of saying before the S3 falling edge, one could
also say before or with the assertion of DSACKx because the
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NOTE
NOTE
IDMA Channels