MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 276

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

System Integration Module (SIM60)
SUPV—Supervisor/User Data Space
6-32
conflicts, external peripherals must not attempt to initiate cycles during show cycles with
arbitration disabled.
The SUPV bit defines the SIM60 global registers as either supervisor data space or user
(unrestricted) data space. It is a don’t care on the SIM60 and is reserved for future expan-
sion.
0 = The SIM60 registers defined as supervisor/user data are unrestricted (FC2 is a
1 = The SIM60 registers defined as supervisor/user are restricted to supervisor data
SHEN1
0
0
1
don’t care).
access (FC3–FC0 = $5). Any attempted user space write is ignored and returns
BERR.
During normal operation, BERR and DSACKx for internal cycles
will not appear as an external cycle in master mode.
For fast termination cycles, DSACKx is never asserted external-
ly regardless of the show cycle bit settings.
In slave mode, these bits default to 00, and writes by the user
have no effect on operation.
In case 00 (show cycles disabled), if the external bus is available
when an internal-to-internal access occurs, the address and
function code pins will reflect the internal access.
Case 01 may be used as a debugging aid to eliminate the exter-
nal bus master as a possible cause of the problem or to prevent
interference in a user debug session.
Although case 00 is recommended for normal operation, case 1x
may be used during initial development for visibility on the inter-
nal bus, at the expense of performance. Moving from 1x to 00 in-
creases performance for two reasons: 1) both the internal and
external buses may be used simultaneously and 2) the external
bus master will obtain the BG signal assertion more quickly after
asserting BR.
SHEN0
0
1
x
Normal operation. Split buses mode. Show cycles is disabled and external arbitration is
enabled.
Show cycles enabled. External arbitration is disabled and BG is never asserted.
Show cycles enabled. External arbitration is enabled and internal activity is halted when
BG is asserted by the QUICC.
Freescale Semiconductor, Inc.
Table 6-3. Show Cycle Control Bits
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
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