MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 196

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

CPU32+
word and SIZ indicates a remaining byte or word. SIZ must be set to long. All other fields
should be left unchanged. The bus controller uses the modified fault address and SIZ field
to rerun the complete released write cycle.
Manipulating the stacked SSW can cause unpredictable results because RTE checks only
the RR bit to determine if a bus cycle must be rerun. Inadvertent alteration of the control bits
could cause the bus cycle to be a read instead of a write or could cause access to a different
address space than the original bus cycle. If the rerun bus cycle is a read, returned data will
be ignored.
5.5.3.2.3 Type II—Correcting Faults via RTE. Instructions aborted because of a type II
fault are restarted upon return from the exception handler. A fault handler must establish
safe restart conditions. If a fault is caused by a nonresident page in a demand-paged virtual
memory configuration, the fault address must be read from the stack, and the appropriate
page retrieved. An RTE instruction terminates the exception handler. After unstacking the
machine state, the instruction is refetched and restarted.
5.5.3.2.4 Type III—Correcting Faults via Software. Sufficient information is contained in
the stack frame to complete MOVEM in software. After the cause of the fault is corrected,
the faulted bus cycle must be rerun. Perform the following procedures to complete an
instruction through software:
A. Set Up for Rerun
B. Rerun Instruction
5-54
1. Read the MOVEM opcode and extension from locations pointed to by stack frame PC
2. Adjust the mask to account for operands already transferred. Subtract the stacked op-
3. Adjust the operand address. If the predecrement addressing mode is in effect, subtract
1. Scan the mask for set bits. Read/write the selected register from/to the operand ad-
2. As each operand is transferred, clear the mask bit and increment (decrement) the op-
3. If the addressing mode is predecrement or postincrement, update the register to com-
4. If TR is set in the stacked SSW, create a six-word stack frame and execute the trace
and PC
is saved in the stack frame. However, the opcode EA field must be examined to deter-
mine how to update the address register and PC when the instruction is complete.
erand transfer count from 16 to obtain the number of operands transferred. Scan the
mask using this count value. Each time a set bit is found, clear it and decrement the
counter. When the count is zero, the mask is ready for use.
the operand size from the stacked value; otherwise, add the operand size to the
stacked value.
dress as each bit is found.
erand address. When all bits in the mask are cleared, all operands have been trans-
ferred.
plete the execution of the instruction.
handler. If either B1 or B0 is set in the SSW, create another six-word stack frame and
execute the hardware breakpoint handler.
2. The EA need not be recalculated since the next operand address
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