MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 461

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

The DPLL is driven by either an external clock or one of the baud rate generator outputs.
This clock should be approximately 8 , 16
encoding/decoding desired. The DPLL uses this clock, along with the data stream, to con-
SCCT DATA
HSRCLK
RXD
TINV
HSTCLK
TENC
TDCR
TEND
Figure 7-45. DPLL Transmit Block Diagram
D
Figure 7-44. DPLL Receive Block Diagram
CK
Freescale Semiconductor, Inc.
For More Information On This Product,
TSNC
RDCR
EDGE
RINV
RXD
HSRCLK
TRANSMITTER
RENC
Q
DPLL
RENC = NRZI
RINV
TENC = NRZI
MC68360 USER’S MANUAL
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ENCODE
0
1
DATA
s
D
RECEIVER
DPLL
X1 MODE
0
1
or 32 times the data rate, depending on the
s
CARRIER SNC
HUNTING
Serial Communication Controllers (SCCs)
NOISE
HSTCLK
HSTCLK
DECODED
D
D
DATA
CK
CK
Q
Q
HSRCLK
HSTCLK
X1 MODE
0
1
s
X1 MODE
0
1
X1 MODE
s
0
1
SCCRDATA
s
RCLK
TCLK
TXEN
TXD