MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 128

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Bus Operation
4.6.1 Bus Request
External devices capable of becoming bus masters request the bus by asserting BR. This
signal can be wire-ORed to indicate to the QUICC that some external device requires control
of the bus. The QUICC is effectively at a lower bus priority level than the external device and
relinquishes the bus after it has completed the current bus cycle (if one has started). If no
BGACK is received while the BR is active, the QUICC remains bus master once BR is
negated. This prevents unnecessary interference with ordinary processing if the arbitration
circuitry inadvertently responds to noise or if an external device determines that it no longer
requires use of the bus before it has been granted mastership.
4-52
DSACK1–DSACK0
BGACK (IN)
NOTE:
Figure 4-36. Bus Arbitration Timing Diagram—Active Bus Case
BG (OUT)
D31–D0
A31–A0
BR (IN)
CLKO1
BR has synchronous timing.
BR has synchronous timing.
R/W
DS
AS
Freescale Semiconductor, Inc.
For More Information On This Product,
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MC68360 USER’S MANUAL
Go to: www.freescale.com
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