MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 664

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Parallel Interface Port (PIP)
TMOD—Timing Mode (Centronics Receiver)
MODL—Mode Low
MODH—Mode High
HSC—Host Control
7-340
When T/R = 1 (PIP is a transmitter), the definition is as follows:
These bits are only valid when T/R is set to receive and MODH is set to pulsed handshake
mode. Otherwise they are ignored.
These bits determine the mode of the PIP’s lower 8 pins (PB7–PB0).
These bits determine the mode of the PIP’s upper 10 pins (PB17–PB8). MODH may be
changed when the RISC processor is not currently receiving or transmitting data.
0 = Ignore the BUSY signal input on PB0 for the transmitter.
1 = Assertion of STB is conditioned by BUSY is negation. STB will not be asserted until
00 = Centronics receiver timing mode 0 (BUSY is negated before ACK is asserted).
01 = Centronics receiver timing mode 1 (BUSY is negated after ACK assertion but be-
10 = Centronics receiver timing mode 2 (BUSY is negated after ACK negation).
11 = Centronics receiver timing mode 3 (BUSY is negated by host software).
00 = Port B general-purpose I/O mode (under host control).
01 = Transparent handshake mode (under RISC or host control).
1x = Mode of operation is controlled by MODH.
00 = Port B general-purpose I/O (under host control).
01 = Transparent handshake mode (under RISC or host control).
10 = Interlocked handshake mode (under RISC or host control).
11 = Pulsed handshake mode (under RISC or host control).
0 = The PIP data transfers are controlled by the RISC in the CPM, using the PIP pa-
1 = The PIP data transfers are controlled by the host software (i.e., CPU32+ or other
the BUSY signal, input on PB0, is negated. EBSY will only take effect if bit 0 of PB-
PAR is 0 to configure this pin to belong to the PIP and bit 0 of PBDIR is 0 to make
this pin an input.
rameter RAM, BDs, and SDMA channels.
external processor in the system).
fore ACK negation).
The programming of MODL has no effect on the BUSY pin if
EBSY is set.
The BUSY pin (PB0) is not affected by MODL programming if
EBSY is set.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
NOTE