MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 440

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Serial Communication Controllers (SCCs)
TCI—Transmit Clock Invert
TSNC—Transmit Sense
RINV—DPLL Receive Input Invert Data
TINV—DPLL Transmit Input Invert Data
7-116
This bit indicates the amount of time the internal sense signal will stay active after the last
transition on the RXD pin, indicating that the line is free. For instance, these bits can be
used in the AppleTalk protocol to avoid the spurious CS-changed interrupt that would oth-
erwise occur during the frame sync sequence that precedes the opening flags.
If RDCR is configured to 1 mode, the delay is the greater of the two numbers listed. If
RDCR is configured to 8 , 16 , or 32 mode, the delay is the lesser of the two numbers
listed.
0 = Normal operation.
1 = The internal transmit clock (TCLK) is inverted by the SCC before it is used. This
00 = Infinite—carrier sense is always active (default)
01 = 14 or 6.5 bit times as determined by the RDCR bits
10 = 4 or 1.5 bit times as determined by the RDCR bits (normally chosen for AppleTalk)
11 = 3 or 1 bit times as determined by the RDCR bits
0 = No invert
1 = Invert the data before it is sent to the on-chip DPLL for reception. This setting is
0 = No invert
1 = Invert the data before it is sent to the on-chip DPLL for transmission. This setting
option allows the SCC to clock data out one-half clock earlier, on the rising edge of
TCLK rather than the falling edge. In this mode, the SCC offers a minimum and
maximum "rising clock edge to data" specification. Data output by the SCC after
the rising edge of an external transmit clock can be latched by the external receiver
one clock cycle later on the next rising edge of the same transmit clock. This option
is recommended for Ethernet, HDLC, or transparent operation when the clock
rates are high (e.g., above 8 MHz) to improve data setup time for the external re-
ceiver.
used to produce FM1 from FM0, NRZI space from NRZI mark, etc. It may also be
used in regular NRZ mode to invert the data stream.
is used to produce FM1 from FM0, NRZI space from NRZI mark, etc. It may also
be used in regular NRZ mode to invert the data stream.
This bit must be 0 in HDLC BUS mode.
This bit must be 0 in HDLC BUS mode.
In T1 applications, setting TINV and TEND creates a continu-
ously inverted HDLC data stream.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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