MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 595

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

descriptions. The part of the SMC parameter RAM that is the same for the UART and trans-
parent SMC protocols is shown in Table 7-12. The following discussion does not apply to
the GCI SMC protocol, which has its own parameter RAM.
Certain parameter RAM values (marked in boldface) need to be initialized by the user before
the SMC is enabled; other values are initialized/written by the CP. Once initialized, most
parameter RAM values will not need to be accessed in user software since most of the activ-
ity is centered around the transmit and receive BDs, not the parameter RAM. However, if
the parameter RAM is accessed by the user, the following restrictions should be noted. The
parameter RAM can be read at any time. The parameter RAMvalues related to the SMC
transmitter can only be written whenever the TEN bit in the SMC mode register is zero, after
a STOP TRANSMIT and before a RESTART TRANSMIT command. The parameter RAM
values related to the SMC receiver can only be written whenever the REN bit in the SMC
mode register is zero or if the receiver has previously been enabled after an ENTER HUNT
MODE command or CLOSE Rx BD command before the REN bit is set.
7.11.4.1 BD TABLE POINTER (RBASE, TBASE). The RBASE and TBASE entries define
the starting location in the dual-port RAM for the set of BDs for receive and transmit func-
tions of the SMC. This provides a great deal of flexibility in how BDs for an SMC are parti-
tioned. By selecting RBASE and TBASE entries for all SMCs, and by setting the W-bit in the
last BD in each BD list, the user may select how many BDs to allocate for the transmit and
receive side of every SMC. The user must initialize these entries before enabling the corre-
SMC Base + 00
SMC Base + 02
SMC Base + 04
SMC Base + 05
SMC Base + 06
SMC Base + 08
SMC Base + 0C
SMC Base + 10
SMC Base + 12
SMC Base + 14
SMC Base + 18
SMC Base + 1C
SMC Base + 20
SMC Base + 22
SMC Base + 24
SMC Base + 28
SMC Base + 36
NOT E: The boldfaced items should be initialized by the user.
Address
Freescale Semiconductor, Inc.
Table 7-12. SMC UART and Transparent
For More Information On This Product,
RSTATE
TSTATE
MRBLR
RBASE
TBASE
RBPTR
TBPTR
Name
RFCR
TFCR
MC68360 USER’S MANUAL
Go to: www.freescale.com
Width
Word
Word
Word
Word
Word
Word
Word
Long
Long
Long
Long
Long
Long
Byte
Byte
Rx Buffer Descriptors Base Address
Tx Buffer Descriptors Base Address
Rx Function Code
Tx Function Code
Maximum Receive Buffer Length
Rx Internal State
Rx Internal Data Pointer
Rx Buffer Descriptor Pointer
Rx Internal Byte Count
Rx Temp
Tx Internal State
Tx Internal Data Pointer
Tx Buffer Descriptor Pointer
Tx Internal Byte Count
Tx Temp
First Word of Protocol Specific Area
Last Word of Protocol Specific Area
Serial Management Controllers (SMCs)
Description