MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 750

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Applications
The SCC status register (SCCS) is also available on the QUICC. The configuration of this
register depends on the protocol mode. In all cases, the CTS and CD bits are available in
the PCDAT register, which allows the user to read the current value of these signals directly
from the pins. Additionally, the ID bit is available in the QUICC SCCS register in UART and
HDLC modes.
The 16-bit SPMODE register consists of two halves: the 8-bit SMC mode register and the 8-
bit SCP mode register.
The SMCs on the QUICC are much more similar to the SCCs on the MC68302. To port an
ISDN (GCI or IOM2) application to the QUICC that uses the MC68302 SCCs, the user
should use the features provided in the serial interface and SMC.
The QUICC does not contain special support for IDL in the SMCs because IDL no longer
uses the A or M bits, but rather uses an out-of-band control bus called the SCP. On the
QUICC, the SCP function may be implemented with the SPI.
The SCP on the QUICC is enhanced to full serial peripheral interface (SPI) functionality. The
SPI is found on many Motorola devices, such as the MC68HC11. The 8-bit SCP mode reg-
ister is most closely related to the 16-bit SPI mode register (SPMODE) on the QUICC.
The SIMASK register on the MC68302 is used in GCI and IDL modes to select individual
bits of the B-channels to be routed to particular SCCs. On the QUICC, the serial interface
has a time slot assigner that is much more flexible and can be used in any time division mul-
tiplexed (TDM) interface, not just GCI and IDL. The time slot assigner on the QUICC is pro-
grammed using a feature called the serial interface RAM. See 7.8.4 SI RAM.
The SIMODE register on the MC68302 controls the serial interface. On the QUICC, the se-
rial interface control is greatly enhanced and is comprised of the serial interface RAM, the
serial interface global mode register (SIGMR), the serial interface mode register (SIMODE),
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The EN bit is in the SPMODE register.
The PM3–PM0 bits are located in the SPMODE register.
The CI bit is located in the SPMODE register.
The LOOP bit is located in the SPMODE register.
The STR bit becomes the R-bit of the SPI transmit buffer descriptor. The buffer descriptor
structure of the SPI is like that of the SCCs.
New status functions are available in the QUICC SCCS, such as
whether the HDLC controller is currently receiving flags and the
DPLL carrier sense status.
On the QUICC, the two SMCs can also provide a UART or totally
transparent control function.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
NOTE