MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 124

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Bus Operation
4.5.4 Double Bus Fault
A double bus fault results when a bus error or an address error occurs during the exception
processing sequence for any of the following:
For example, the QUICC attempts to stack several words containing information about the
state of the machine while processing a bus error exception. If a bus error exception occurs
during the stacking operation, the second error is considered a double bus fault. When a
double bus fault occurs, the QUICC halts and drives the HALT line low. Only a reset opera-
tion can restart a halted QUICC. However, bus arbitration can still occur (refer to 4.6 Bus
Arbitration). A second bus error or address error that occurs after exception processing has
4-48
1. A previous bus error
2. A previous address error
3. A reset
FC3–FC0
DSACKx
D31–D0
A31–A0
BGACK
CLKO1
HALT
R/W
DS
BR
BG
AS
S0
Freescale Semiconductor, Inc.
For More Information On This Product,
S2
READ
Figure 4-33. HALT Timing
MC68360 USER’S MANUAL
S4
Go to: www.freescale.com
WHILE THE PROCESSOR IS
(ARBITRATION PERMITTED
HALTED)
HALT
S0
S2
READ
S4
S0