MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 566

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
Serial Communication Controllers (SCCs)
In either mode, an interrupt can be issued according to the I-bit in the Tx BD. The Ethernet
controller will then proceed to the next Tx BD in the table. In this way, the user may be inter-
rupted after each frame, after each buffer, or after a specific buffer has been transmitted.
The Ethernet controller has an option to add pad characters to short frames. If the PAD bit
is set in the Tx BD, the frame will be padded up to the value of the minimum frame length
register.
To rearrange the transmit queue before the CP has completed transmission of all frames,
issue the GRACEFUL STOP TRANSMIT command. This technique can be useful for trans-
mitting expedited data before previously linked buffers or for error situations. When the
GRACEFUL STOP TRANSMIT command is issued, the Ethernet controller will stop imme-
diately if no transmission is in progress, or continue transmission until the current frame has
successfully completed transmission or terminates with a collision. When the Ethernet con-
troller is given the RESTART TRANSMIT command, it resumes transmission.
The Ethernet controller transmits bytes LSB first.
7.10.23.6 ETHERNET CHANNEL FRAME RECEPTION. The Ethernet receiver is also
designed to work with almost no intervention from the host. The Ethernet receiver can per-
form address recognition, CRC checking, short frame checking, maximum DMA transfer
checking, and maximum frame length checking.
When the host enables the Ethernet receiver, it will enter hunt mode as soon as the RENA
signal is asserted if CLSN is negated. In hunt mode, as data is shifted into the receive shift
register one bit at a time, the contents of the register are compared to the contents of the
SYN1 field in the data synchronization register. This compare function becomes valid a cer-
tain number of clocks after the start of the frame (depending on the NIB bits in the PSMR).
If the two are not equal, the next bit is shifted in, and the comparison is repeated. If a double
zero fault or double one fault is detected between bits 14 to 21 from the start of the frame,
the frame is rejected. If a double zero fault is detected after 21 bits from the start of the frame
and before detection the start frame delimiter, the frame is also rejected. When the registers
match, the hunt mode is terminated, and character assembly begins.
When the receiver detects the first bytes of the frame, the Ethernet controller will perform
address recognition functions on the frame (see 7.10.23.11 Ethernet Address Recognition).
The receiver can receive physical (individual), group (multicast), and broadcast addresses.
No Ethernet receive frame data is written to memory until the internal address recognition
algorithm is complete, which improves bus utilization in the case of frames not addressed to
this station.
The receiver can also work with an external CAM. See 7.10.23.7 CAM Interface for more
details. In the case of an external CAM, frame reception continues normally unless the CAM
specifically signals the frame to be rejected.
If a match is detected, the Ethernet controller will fetch the next Rx BD and, if it is empty, will
start to transfer the incoming frame to the Rx BD’s associated data buffer. If a collision is
detected during the frame, the Rx BDs associated with this frame are reused. Thus, no col-
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MC68360 USER’S MANUAL
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