MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 497

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

C_MASK. For the 16-bit CRC-CCITT, C_MASK should be initialized with $0000F0B8. For
the 32-bit CRC-CCITT, C_MASK should be initialized with $DEBB20E3.
C_PRES. For the 16-bit CRC-CCITT, C_PRES should be initialized with $0000FFFF. For
the 32-bit CRC-CCITT, C_PRES should be initialized with $FFFFFFFF.
DISFC, CRCEC, ABTSC, NMARC, and RETRC. These 16-bit (modulo 2 16 ) counters are
maintained by the CP. They may be initialized by the user while the channel is disabled. The
counters are as follows:
MFLR. The HDLC controller checks the length of an incoming HDLC frame against the user-
defined value given in this 16-bit register. If this limit is exceeded, the remainder of the
incoming HDLC frame is discarded, and the LG (Rx frame too long) bit is set in the last BD
belonging to that frame. The HDLC controller waits to the end of the frame and reports the
frame status and the frame length in the last Rx BD. MFLR is defined as all the in-frame
bytes between the opening flag and the closing flag (address, control, data, and CRC).
MAX_cnt is a temporary down-counter used to track the frame length.
HMASK, HADDR1, HADDR2, HADDR3, and HADDR4. Each HDLC controller has five 16-
bit registers for address recognition—one mask register and four address registers. The
HDLC controller reads the frame’s address from the HDLC receiver, checks it against the
four address register values, and then masks the result with the user-defined mask register.
A one in the mask register represents a bit position for which address comparison should
DISFC
CRCEC
ABTSC
NMARC
RETRC
NOTE: The boldfaced items should be initialized by the user.
SCC Base + 40
SCC Base + 42
SCC Base + 44
SCC Base + 46
SCC Base + 48
SCC Base + 4A
SCC Base + 4C
SCC Base + 4E
SCC Base + 50
SCC Base + 52
SCC Base + 54
SCC Base + 56
SCC Base + 58
SCC Base + 5A
Discarded Frame Counter (error-free frames but no free buffers)
CRC Error Counter (includes frames not addressed to the user or
frames received in the BSY condition, but does not include overrun
errors)
Abort Sequence Counter
Non-Matching Address Received Counter (error-free frames only)
Frame Retransmission Counter (due to collision)
Freescale Semiconductor, Inc.
Table 7-8. HDLC-Specific Parameters
For More Information On This Product,
MAX_cnt
HADDR1
HADDR2
HADDR3
HADDR4
TMP_MB
NMARC
HMASK
RETRC
RFTHR
RFCNT
ABTSC
MFLR
TMP
MC68360 USER’S MANUAL
Go to: www.freescale.com
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Abort Sequence Counter
Nonmatching Address Rx Counter
Frame Retransmission Counter
Max Frame Length Register
Max_Length Counter
Received Frames Threshold
Received Frames Count
User-Defined Frame Address Mask
User-Defined Frame Address
User-Defined Frame Address
User-Defined Frame Address
User-Defined Frame Address
Temp Storage
Temp Storage
Serial Communication Controllers (SCCs)