MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 463

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

7.10.13 Clock Glitch Detection
A clock glitch occurs when an input clock signal transitions between a one and zero state
twice, within a small enough time period to violate the minimum high/low time specification
of the input clock. Spikes are one type of glitch. Additionally, glitches can occur when exces-
sive noise is present on a slowly rising/falling signal.
Glitched clocks are a worry to many communications systems. Not only can they cause sys-
tems to experience errors, they can potentially cause errors to occur without even being
detected by the system. Systems that supply an external clock to a serial channel are often
susceptible to glitches from situations such as noise, connecting/disconnecting the physical
cable from the application board, or excessive ringing on the clock lines.
The SCCs on the QUICC have a special circuit designed to detect glitches that may occur
in the system. The glitch circuit is designed to detect glitches that could cause the SCC to
transition to the wrong state. This status information can be used to alert the system of a
problem at the physical layer.
The glitch detect circuit is not a specification test. Thus, if the user develops a circuit that
does not meet the input clocking specifications for the SCCs, erroneous data may be
received/transmitted that is not indicated by the glitch detection logic. Conversely, if a glitch
indication is signaled, it does not guarantee that erroneous data was received/transmitted.
Regardless of whether the DPLL is used, the received clock is passed through a noise filter
that eliminates any noise spikes that affect a single sample. This sampling is enabled with
the GDE bit of the GSMR.
If a spike is detected, a maskable receive or transmit glitched clock interrupt is generated in
the event register of the SCC channel. Although the user may choose to reset the SCC
receiver or transmitter or to continue operation, he should keep statistics on clock glitches
for later evaluation. In addition, the glitched status indication may be used as a debugging
aid during the early phases of prototype testing.
7.10.14 Disabling the SCCs on the Fly
If an SCC is not needed for a period of time, it may be disabled and reenabled later. In this
case, a sequence of operations is followed.
These sequences ensure that any buffers in use will be properly closed and that new data
will be transferred to/from a new buffer. Such a sequence is required if the parameters that
must be changed are not allowed to be changed dynamically. If the register or bit description
The 1:2 ratio of the SyncCLK to the serial clock does not apply
when the DPLL is used to recover the clock in the 8 , 16 , or 32
modes. The synchronization actually occurs internally after the
receive clock is generated by the DPLL; therefore, even the fast-
est DPLL clock generation (the 8 option) easily meets the re-
quired 1:2 ratio clocking limit.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
Serial Communication Controllers (SCCs)