MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 384

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

SDMA Channels
Bits 15, 12, 11, 7, 2—Reserved
FRZ1–FRZ0—Freeze
SISM—SDMA Interrupt Service Mask
SAID—SDMA Arbitration ID
INTE—Interrupt Error
7-60
15
—
These bits determine the action to be taken when the FREEZE signal is asserted. The
SDMA negates BR and keeps it negated until FREEZE is negated or a reset occurs.
These bits contain the interrupt service mask. When the interrupt service level on the IMB
is greater than the interrupt service mask, the SDMA relinquishes the bus and negates
the internal bus request to the IMB until the interrupt level service is less than or equal to
the interrupt service mask.
These bits establish bus arbitration priority level among modules that have the capability
of becoming bus master. In the QUICC, the DRAM refresh controller, IDMAs, SDMAs, and
external bus masters can obtain bus mastership. The SDMA channel arbitration ID is de-
termined by these bits. Zero is the lowest priority, and seven is the highest priority.
This bit enables the SBER status bit in the SDSR.
00 = The SDMA channels ignore the FREEZE signal.
01 = Reserved.
10 = The SDMA channels freeze on the next bus cycle.
11 = Reserved.
0 = A zero masks the interrupt generated by the corresponding bit in the SDSR. If a
1 = If a bus error occurs while the SDMA is bus master, the channel generates an in-
14
bus error occurs while the SDMA is bus master, the channel does not generate an
interrupt to the QUICC interrupt controller. The SBER bit is still set in the SDSR.
terrupt to the QUICC interrupt controller and sets the SBER bit in the SDSR.
FRZ
13
This value should be programmed to 7 for typical user applica-
tions. This level gives the SDMA channels priority over all inter-
rupt handlers.
This value should be programmed to 4 for typical user applica-
tions. This value should always be programmed to a value larger
than the arbitration IDs for the two IDMA channels. The user
must program this field to 7 when the QUICC is configured in
slave mode.
12
—
11
Freescale Semiconductor, Inc.
For More Information On This Product,
10
MC68360 USER’S MANUAL
Go to: www.freescale.com
SISM
9
NOTE
NOTE
8
—
7
6
SAID
5
4
3
—
2
INTE
1
INTB
0