MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 567

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Freescale Semiconductor, Inc.
Serial Communication Controllers (SCCs)
lision frames are presented to the user except late collisions, which indicate serious LAN
problems.
When the data buffer has been filled, the Ethernet controller clears the E-bit in the Rx BD
and generates an interrupt if the I-bit is set. If the incoming frame exceeds the length of the
data buffer, the Ethernet controller will fetch the next Rx BD in the table and, if it is empty,
will continue to transfer the rest of the frame to this BD’s associated data buffer.
The Rx BD length is determined in the MRBLR value in the SCC general-purpose parameter
RAM. The user should program MRBLR to be at least 64 bytes.
During reception, the Ethernet controller will check for a frame that is too short or too long.
When the frame ends (carrier sense is negated), the receive CRC field is checked and writ-
ten to the data buffer. The data length written to the last BD in the Ethernet frame is the
length of the entire frame. This enables software to correctly recognize the frame-too-long
condition.
When the receive frame is complete, the Ethernet controller has the option to sample one
byte from the port B parallel I/O (PB15–PB8) and append this byte to the end of the last Rx
BD in the frame. For any of the PB15–PB8 pins that are defined as outputs, the contents of
the PBDAT latch is read, rather than the pin itself. Although this capability is useful for CAM
applications, it may be used whether or not an external CAM is present. The sampling
occurs at the end of frame reception.
The Ethernet controller then sets the L-bit in the Rx BD, writes the other frame status bits
into the Rx BD, and clears the E-bit. The Ethernet controller next generates a maskable
interrupt, indicating that a frame has been received and is in memory. The Ethernet control-
ler then waits for a new frame.
The Ethernet controller receives serial data LSB first.
7.10.23.7 CAM INTERFACE. The Ethernet controller has two options for connecting to an
external CAM: a serial interface option and a system bus interface option. Actually, both
options may be used at once (there is no mode bit to select them); however, they are
described independently for clarity. To implement an option, the user only needs to enable
the particular pins that are desirable.
Both options use a reject pin on the QUICC to signify that the current frame is to be dis-
carded. The QUICC internal address recognition logic may be used in combination with an
external CAM. See 7.10.23.11 Ethernet Address Recognition for more details.
The serial interface option is shown in Figure 7-66. The QUICC outputs a receive start
(RSTRT) signal when the start frame delimiter is recognized. The RSTRT signal is asserted
for just one bit time on the second destination address bit.
MC68360 USER’S MANUAL
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