MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 781

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

Applications
9.6.4 Functional Description
The 53C90 SCSI controller consists of three major sections: the processor interface, the
data path, and the logic block. The processor interface includes the 8-bit data bus, parity bit,
chip select, read/write strobes, A0–A3 address lines, interrupt request, and DMA signals.
The data path consists of a 16-byte FIFO, parity generation, DMA interface, and SCSI data
and control bus inputs/outputs.
The logic block consists of a hierarchy of sequencers that direct the SCSI bus control signal
timing. The 53C90 has a set of on-chip state machines that directly perform many SCSI
sequences. The instruction sequencer and master sequencer provide control of these state
machines. Since the 53C90 has no real decision-making capability, it relies on the CPU32+
for supervisory control and for integrating the performed SCSI sequences into complete
operations. Processor service is requested through a standard interrupt structure, and the
53C90 reports the status through its register set.
Overall control of the 53C90 is done through the processor interface. The processor data
bus and associated control signals provide the means to initialize and set the operating
mode of the SCSI as well as provide the data path for information swapping. The processor
can write to a set of 12 registers, instructing the 53C90 what function to perform, then read
another set of registers to determine the status.
Once the 53C90 starts executing, all data transfers are handled by the DMA. Since the
53C90 does not have an onboard DMA controller, it relies on one of the two independent
DMA (IDMA) channels of the QUICC. In this case, IDMA1 is arbitrarily chosen. IDMA1 of the
QUICC moves the data to and from the 53C90 FIFO. The FIFO provides a 9-bit-wide by 16-
byte-deep buffer. It can be accessed by either the IDMA or the processor at register address
$02 and can be read or written as a register. The bottom of the FIFO is read and unloaded
while the top is written to and loaded.
Therefore, for an SCSI transfer to occur, the processor has to initialize the 53C90 by writing
to its registers, initialize IDMA1 by setting up its registers, and then monitor the status of the
53C90.
Table 9-2 lists the read and write registers in the 53C90.
9-61
Address (Hex)
$0C-$0F
$0A
$0B
$00
$01
$03
$04
$05
$06
$07
$08
$09
$02
Table 9-3. 53C90 Read and Write Registers
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Transfer Counter MSB
Go to: www.freescale.com
Transfer Counter LSB
FIFO Flags/Seq. Step
Instruction Executing
Sequence Step
Configuration 1
Configuration 2
Read Register
Reserved
Reserved
Reserved
Interrupt
Status
FIFO
Clock Conversion (Presel)
Select/Reselect Timeout
Transfer Counter MSB
Transfer Counter LSB
Synchronous Period
Synchronous Offset
Instruction Holding
Write Register
Configuration 1
Configuration 2
Destination ID
Test Mode
Reserved
FIFO