MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 182

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

CPU32+
5.5.2 Processing of Specific Exceptions
The following paragraphs provide details concerning sources of specific exceptions, how
each arises, and how each is processed.
5.5.2.1 RESET. Assertion of RESET by external hardware or assertion of the internal RE-
SET signal by an internal module causes a reset exception. The reset exception has the
highest priority of any exception. Reset is used for system initialization and for recovery from
catastrophic failure. When the reset exception is recognized, it aborts any processing in
progress, and that processing cannot be recovered. Reset performs the following opera-
tions:
Figure 5-11 is a flowchart of the reset exception
After initial instruction prefetches, normal program execution begins at the address in the
PC. The reset exception does not save the value of either the PC or the SR.
If a bus error or address error occurs during reset exception processing, a double bus fault
occurs, the processor halts, and the HALT signal is asserted to indicate the halted condition.
Execution of the RESET instruction does not cause a reset exception nor does it affect any
internal CPU register. The SIM60 registers and the module control register in each internal
peripheral module (DMA, timers, and serial modules) are not affected. All other internal
peripheral module registers are reset the same as for a hardware reset. The external
devices connected to the RESET signal are reset at the completion of the reset instruction
5.5.2.2 BUS ERROR. A bus error exception occurs when an assertion of the BERR signal
is acknowledged. The BERR signal can be asserted by one of three sources:
Bus error exception processing begins when the processor attempts to use information from
an aborted bus cycle.
5-40
1. Clears T0 and T1 in the SR to disable tracing
2. Sets the S-bit in the SR to establish supervisor privilege
3. Sets the interrupt priority mask to the highest priority level (%111)
4. Initializes the VBR to zero ($00000000)
5. Generates a vector number to reference the reset exception vector
6. Loads the first long word of the vector into the interrupt SP
7. Loads the second long word of the vector into the PC
8. Fetches and initiates decode of the first instruction to be executed
1. External logic by assertion of the BERR input pin
2. Direct assertion of the internal BERR signal by an internal module
3. Direct assertion of the internal BERR signal by the on-chip hardware watchdog
after detecting a no-response condition
Freescale Semiconductor, Inc.
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