MC68EN360AI25VL Freescale, MC68EN360AI25VL Datasheet - Page 649

• Manufacturer Part Number: MC68EN360AI25VL
• Manufacturer: Freescale

Specifications of MC68EN360AI25VL

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Supply Voltage (max): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Lead Free Status / RoHS Status: Compliant

The following bits should be written by the CPU32+ core before enabling the SPI.
E—Empty
Bits 14, 10, 8–2—Reserved
W—Wrap (Final BD in Table)
I—Interrupt
CM—Continuous Mode
This bit is valid only when the SPI is configured as a master; it should be written as a zero
in slave mode.
OFFSET + 0
OFFSET + 2
OFFSET + 4
OFFSET + 6
0 = The data buffer associated with this Rx BD has been filled with received data, or
1 = The data buffer associated with this BD is empty, or reception is currently in
0 = This is not the last BD in the Rx BD table.
1 = This is the last BD in the Rx BD table. After this buffer has been used, the CP will
0 = No interrupt is generated after this buffer has been filled.
1 = The RXB bit in the SPI event register will be set when this buffer has been com-
0 = Normal operation.
1 = The E-bit is not cleared by the CP after this BD is closed, allowing the associated
data reception has been aborted due to an error condition. The CPU32+ core is
free to examine or write to any fields of this Rx BD. The CP will not use this BD
again while the E-bit remains zero.
progress. This Rx BD and its associated receive buffer are owned by the CP. Once
the E-bit is set, the CPU32+ core should not write any fields of this Rx BD.
receive incoming data into the first BD in the table (the BD pointed to by RBASE).
The number of Rx BDs in this table is programmable and is determined only by the
W-bit and the overall space constraints of the dual-port RAM.
pletely filled by the CP, indicating the need for the CPU32+ core to process the
buffer. The RXB bit can cause an interrupt if it is enabled.
data buffer to be overwritten automatically when the CP next accesses this BD.
This allows continuous reception from an SPI slave into one buffer for autoscan-
ning of a serial A/D peripheral with no CPU overhead.
15
E
14
—
13
W
Freescale Semiconductor, Inc.
For More Information On This Product,
12
I
11
L
MC68360 USER’S MANUAL
Go to: www.freescale.com
10
—
CM
RX DATA BUFFER POINTER
9
DATA LENGTH
—
8
—
7
—
6
—
5
Serial Peripheral Interface (SPI)
—
4
—
3
—
2
OV
1
ME
0