IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 92

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

PCI Bus Signals
3–18
PCI Compiler User Guide
l_adro[63..0]
l_dato[63..0]
l_beno[7..0]
Table 3–6. PCI Local Address, Data, Command & Byte Enable Signals (Part 2 of 3)
Name
Output
Output
Output
Type
–
–
–
Polarity
PCI Compiler Version 10.1
Local address output. The l_adro[63..0] bus is driven by the PCI
MegaCore functions during target transactions. The pci_mt32 and
pci_t32 functions only implement l_adro[31..0]. During dual address
transactions in the pci_mt64 and pci_t64 MegaCore functions, the
l_adro[63..32] bus is driven with a valid address. DAC is indicated by
the assertion of lt_tsr[11]. For more information on the local target
status signals, refer to
The falling edge of lt_framen indicates a valid l_adro[63..0]. The PCI
address is held at the local side as long as possible and should be
assumed invalid at the end of the target transaction on the PCI bus.
The end of the target transaction is indicated by lt_tsr[8] (targ_access)
being deasserted.
Local data output. The
PCI bus-initiated target write transactions or local side-initiated master
read transactions. The functionality of this bus changes depending on
the function you are using and the transaction being considered. The
pci_mt32
l_dato[31..0]
MegaCore functions is dependent on the type of transaction being
considered. During 64-bit target write transactions and master read
transactions, the data is transferred on the entire
bus. During 32-bit master read transactions, the data is only
transferred on
transactions, the data is also only transferred on
however, depending on the transaction address, the
pci_t64
l_hdat_ackn
word is a
Local byte enable output. The
PCI function during target transactions. This bus holds the byte enable
value during data transfers. The functionality of this bus is different
depending on the function being used and the transaction being
considered. The
l_beno[3..0]
MegaCore functions is dependent on the type of transaction being
considered. During 64-bit target write transactions, the byte enables
are transferred on the entire
target write transactions, the byte enables are transferred on the
l_beno[3..0]
pci_mt64
l_ldat_ackn
for the current byte enables is at a
B"000"
) or not.
QWORD
MegaCore function either asserts
and
or
l_dato[31..0]
pci_t64
to indicate whether the address for the current data
or
pci_t32
pci_mt32
. The operation in the
boundary (
bus and, depending on the transaction address, the
. The operation in the
l_hdat_ackn
Table
l_dato[63..0]
MegaCore function either asserts
functions implement only
ad[2..0] = B"000"
Description
l_beno[7..0]
3–8.
and
l_beno[7..0]
pci_t32
. During 32-bit target write
QWORD
to indicate whether the address
pci_mt64
pci_mt64
bus is driven active during
boundary (
functions implement only
l_ldat_ackn
bus. During 32-bit
bus is driven by the
l_dato[31..0]
l_dato[63..0]
Altera Corporation
and
pci_mt64
and
) or not.
ad[2..0] =
January 2011
pci_t64
pci_t64
or
or
;