IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 315

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Control & Status
Registers
Altera Corporation
January 2011
The Avalon-MM interrupt status register contains two bits that indicate
whether a rising- or falling-edge is detected on intan. Similarly, the
Avalon-MM interrupt enable register has two bits that enable the
signaling of an Avalon-MM interrupt on either a rising- or falling-edge of
the Avalon-MM interrupt enable register. For a complete description of
the Avalon-MM interrupt status register and Avalon-MM interrupt
enable register, refer to
page
MSI interrupts can be received by using the PCI-to-Avalon mailbox
registers - read/write as the target of the PCI MSI messages. MSI
interrupts can also be received by another Avalon-MM slave specifically
designed to process them.
Generation of Avalon-MM Interrupts
Avalon-MM interrupts (the CraIrq_o signal) can be generated by a
variety of error conditions, mailbox writes, or PCI interrupt signals. For a
complete list of Avalon-MM interrupts, refer to the Avalon-MM interrupt
status register
enable register
These registers are accessible from the Control Register Access
Avalon Slave port. If you do not enable the Control Register
Access Avalon Slave port (refer to
page
The control and status register space is spread over a 16-KByte region,
with each 4-KByte sub-region containing a specific set of functions that
may be specific to accesses from either:
■
■
■
PCI processors only
Avalon processors only
From both types of processors
7–60.
6–16), none of the control and status registers will be implemented.
PCI Compiler Version 10.1
(Table 7–26 on page
(Table 7–28 on page
Table 7–26 on page 7–57
7–57) and the Avalon-MM interrupt
7–60).
“Avalon Configuration” on
and
Functional Description
Table 7–28 on
7–47