IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 322

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Control & Status Registers
7–54
PCI Compiler User Guide
Note to
(1)
0x1000
0x1004
0x1008
0x100C
Table 7–22. Avalon-to-PCI Address Translation Table – Address Range: 0x1000-0x1FFF
Address
The above table entries are repeated for the number of pages you selected in the Avalon configuration tab
I
A2P_ADDR_MAP_LO511 and 0x1FFC will contain A2P_ADDR_MAP_HI511. Refer to
Configuration” on page
f the Number of Address Pages field is set to the maximum of 512, then 0x1FF8 will contain
Table
1:0
31:2
31:0
1:0
31:2
31:0
Bit
7–22:
A2P_ADDR_SPACE0
A2P_ADDR_MAP_LO0
A2P_ADDR_MAP_HI0
A2P_ADDR_SPACE1
A2P_ADDR_MAP_LO1
A2P_ADDR_MAP_HI1
6–16.
Name
The lower order address bits that are treated as a pass through between
Avalon-MM and PCI, and the number of pass-through bits, are defined
by the size of page in the address translation table and are always forced
to 0 in the hardware table. For example, if the page size is 4 KBytes, the
number of pass-through bits is log
Read-Only Configuration Registers
These registers reflect some of the configuration parameters that enable
the software to understand the configuration of the PCI-Avalon bridge.
Providing this information in these registers allows the software to adapt
to the bridge configuration at run time without specifying the same
parameter settings to the software at compilation time.
PCI Compiler Version 10.1
RW
RW
RW
RW
RW
RW
Access
Mode
Address space indication for entry 0. Refer to
Table 7–12 on page 7–37
Lower bits of Avalon-to-PCI address map entry 0. The
pass through bits are not writable and are forced to 0.
Upper bits of Avalon-to-PCI address map entry 0.
When the PCI bus width is 32 bits, these bits are not
writable and are forced to 0.
Address Space indication for entry 1. Refer to
Table 7–12 on page 7–37
Lower bits of Avalon-to-PCI address map entry 1. Pass
through bits are not writable and are forced to 0.
This entry is only implemented if the number of pages
in the address translation table is greater than 1.
Upper bits of Avalon-to-PCI address map entry 1.
When the PCI bus width is 32 bits, these bits are not
writable and are forced to 0.
This entry is only implemented if the number of pages
in the address translation table is greater than 1.
2
(page size) = log
Description
for the definition of these bits.
for the definition of these bits.
2
(4 KBytes) = 12.
Altera Corporation
“Avalon
Note (1)
January 2011
.