IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 115

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
0
10..1
31..11
Table 3–28. Expansion ROM Base Address Register Format
Data
Bit
adr_ena
Reserved
bar
Mnemonic
Read/write
–
Read/write
Read/Write
Subsystem ID Register
The subsystem ID register identifies the subsystem. The value of this
register is defined by the subsystem vendor, i.e., the designer. Refer to
Table
However, you can change the value through the wizard.
Expansion ROM Base Address Register
The expansion ROM base address register contains a 32-bit hexadecimal
number that defines the base address and size information of the
expansion ROM. Instantiate the expansion ROM BAR using the
Parameterize - PCI Compiler wizard. The expansion ROM BAR
functions exactly like a 32-bit BAR, except that the encoding of the bottom
bits is different. Bit 0 in the register is a read/write and is used to indicate
whether or not the device accepts accesses to its expansion ROM. You can
disable the expansion ROM address space by setting bit 0 to 0. You can
enable the address decoding of the expansion ROM by setting bit 0 to 1.
The upper 21 bits correspond to the upper 21 bits of the expansion ROM
base address. The amount of address space a device requests must not be
greater than 16 Megabytes (MBytes). The expansion ROM BAR is
formatted per the PCI Local Bus Specification, Revision 3.0. Refer to
Table
Table 3–27. Subsystem ID Register Format
Data Bit
15..0
3–27. The default value of the subsystem ID register is 0x0000.
3–28.
Address decode enable. The
device accepts accesses to its expansion ROM. You can disable the
expansion ROM address space by setting this bit to 0. You can enable the
address decoding of the expansion ROM by setting this bit to 1.
–
Expansion ROM base address registers.
PCI Compiler Version 10.1
Mnemonic
sub_id
adr_ena
Read/Write
Definition
Read
bit indicates whether or not the
Functional Description
PCI subsystem ID
Definition
3–41