IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 263

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
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BAR Size—The BAR size must be set to encompass the addresses of all the
Avalon-MM peripherals that you wish to access with the BAR. The BAR
size must be greater than or equal to the range of Avalon-MM address
that it accesses.
You can configure the BAR size either manually or automatically. To
automatically set the BAR size, select Auto for BAR size. Auto will
automatically set the BAR size to encompass the entire address space for
the Avalon-MM peripherals that are addressed by the BAR.
Avalon Base Address—The Avalon-MM base address corresponds to the
PCI base address. Based on the BAR size setting, the PCI-Avalon bridge
replaces the PCI base address with the Avalon-MM base address. In other
words, the read/write bits of the PCI Base Address Register are replaced
with the equivalent Avalon-MM base address bits.
You can configure the Avalon-MM base address either manually or
automatically. To automatically set the Avalon-MM base address, select
Auto for the BAR size. Refer to
Base Address”
in this BAR type to 2 GBytes. In other words, this BAR type allows
your device to reside anywhere in the 64-bit address space, but does
not allow you to reserve more than 2 GBytes.
Only one 64-bit prefetchable BAR is allowed in a system. All other
BARs you define are 32-bit BARs.
32-Bit Non-Prefetchable Memory: Non-prefetchable memory
address is normally used for register or memory space where the
read operation can modify the state of the data you read.
Implementing one or more 32-bit non-prefetchable BARs enables a
non-prefetchable master port for the PCI-Avalon bridge. If the
transaction address matches a non-prefetchable memory BAR, only
single cycle transactions for both read and write operations are
performed.
I/O: Implementing at least one IO BAR enables a non-prefetchable
master port for the PCI-Avalon bridge. Only single-cycle reads and
writes are supported. All I/O reads and writes are non-posted, and
handled as delayed operations. The amount of address space a
device requests can range between 4 and 256 bytes, inclusively. I/O
address space decoding for legacy devices is supported, as described
in Appendix G of the PCI Specifications.
PCI Compiler Version 10.1
for information on setting the size of the BAR.
“Manual Setting of the BAR Size & Avalon
Parameter Settings
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