IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 222

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Testbench Specifications
4–12
PCI Compiler User Guide
io_wr
The io_wr command performs a single-cycle memory write transaction
with the address and data provided in the command arguments.
io_rd
The io_rd command performs single-cycle I/O read transactions with
the address provided in the command argument.
Target Transactor (trgt_tranx)
The target transactor simulates the behavior of a target agent on the PCI
bus. The master transactions initiated by the Altera PCI MegaCore
function under test should be addressed to the target transactor. The
target transactor operates in 32- or 64-bit mode. The target transactor
implements two base address registers BAR0 and BAR1 as shown in
Table
For definitions of the target transactor address space, refer to the base
address registers in
The memory range reserved by BAR0 is defined by the address_lines
and mem_hit_range settings in the target transactor source code.
The target transactor has a 32-bit register that stores data for I/O
transactions. This register is mapped to BAR1 of the configuration
address space. Because this is the only register that is mapped to BAR1,
Syntax:
Arguments:
Syntax:
Arguments:
Table 4–7. Target Transactor Address Space Allocation
Configuration
Register
4–7.
BAR0
BAR1
PCI Compiler Version 10.1
io_rd(address)
address
io_wr(address, data)
address
data
Memory Mapped
Table 4–8, “Memory Map,” on page 16.
Address Space
I/O Mapped
Type
Transaction address. This value must be in
hexadecimal radix.
Transaction address. This value must be
in hexadecimal radix.
Data written during the transaction. This
value must be in hexadecimal radix.
Block Size
16 Bytes
1 KByte
Altera Corporation
Address Offset
January 2011
000-3FF
0-F