IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 226

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Local Reference Design
Figure 4–3. Local Reference Design
Note to
(1)
4–16
PCI Compiler User Guide
BAR0
BAR1
BAR2
Memory Region
Table 4–8. Memory Map
Testbench
Modules
The DMA Engine, lm_lastn and local master blocks are not applicable for the pci_t32 and pci_t64 local reference
designs.
Figure
4–3:
PCI Bus
Memory Mapped 1 KByte
I/O Mapped
Memory Mapped 1 KByte
Mapping
MegaCore
Altera PCI
Function
Table 4–8
required to use the local reference design.
The reference design has the following elements:
■
■
■
■
■
■
Local target
DMA engine
Local master
lm_lastn generator
Prefetch
LPM RAM
Block size Address Offset
16 Bytes
shows the memory map of the Altera PCI MegaCore function
PCI Compiler Version 10.1
000-3FF
0-F
000-3FF
lm_lastn (1)
Master (1)
Target
Local
Local
Maps the LPM_RAM function.
Maps the I/O register.
Maps the
DMA engine registers. Only the lower 24
Bytes of the address space are used.
trg_termination
Description
Local Reference Design
DMA Engine (1)
Altera Corporation
LPM RAM
dma_bc_la
Prefetch
dma_sa
January 2011
register and