IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 193

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 3–42. Burst Memory Write Master Transaction with Variable Byte Enables
Notes to
(1)
(2)
Altera Corporation
January 2011
This signal is not applicable to the pci_mt32 MegaCore function.
For pci_mt32, lm_req32n should be substituted for lm_req64n for 32-bit master transactions.
(1), (2) lm_req64n
(1) l_adi[63..32]
(1) l_cbeni[7..4]
(1) l_hdat_ackn
(1) l_ldat_ackn
(1) ad[63..32]
(1) cben[7..4]
lm_adr_ackn
l_cbeni[3..0]
l_adi[31..0]
lm_tsr[9..0]
Figure
(1) ack64n
(1) req64n
cben[3..0]
(1) par64
ad[31..0]
lm_dxfrn
lm_lastn
lm_ackn
lm_rdyn
devseln
framen
stopn
irdyn
trdyn
reqn
gntn
par
clk
3–42:
1
000
2
32-Bit Single-Cycle Memory Write Master Transactions
Figure 3–43
The transaction shown in
Figure
data word. This figure applies to both the pci_mt64 and pci_mt32
MegaCore functions, excluding the 64-bit extension signals as noted for
pci_mt32.
3
001
4
3–39, except that the local side master interface transfers only one
PCI Compiler Version 10.1
shows a 32-bit single-cycle memory write master transaction.
5
Adr
002
0
0
0
0
7
6
BE0_H
BE0_L
D0_L
D0_H
Adr
004
7
7
Figure 3–43
Adr-PAR
008
BE0_H
BE1_H
BE0_L
BE1_L
D0_L
D0_H
D1_H
D1_L
8
208
D0-H-PAR
D0-L-PAR
9
is the same as that shown in
BE1_H
BE1_L
BE2_H
BE2_L
D2_L
D2_H
D1_H
D1_L
10
D1-H-PAR
D1-L-PAR
BE2_L
BE3_H
BE3_H
BE3_L
D3_L
D3_H
D2_H
D2_L
11
308
Functional Description
D2-H-PAR
D2-L-PAR
BE3_L
BE3_H
D3_H
D3_L
12
D3-H-PAR
D3-L-PAR
Z
Z
Z
Z
13
000
3–119