IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 156

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Target Mode Operation
Figure 3–26. Single Cycle Disconnect in a Burst Read Transaction
Note to
(1)
3–82
PCI Compiler User Guide
(1) l_adi[63..32]
(1) ad[63..32]
This signal is not applicable to either the pci_mt32 or pci_t32 MegaCore functions.
(1) cben[7..4]
l_adro[31..0]
l_cmdo[3..0]
lt_tsr[11..0]
l_adi[31..0]
(1) ack64n
(1) req64n
cben[3..0]
lt_framen
(1) par64
ad[31..0]
Figure
devseln
lt_discn
lt_dxfrn
framen
lt_ackn
lt_rdyn
stopn
trdyn
irdyn
par
clk
3–26:
1
2
000
Adr
Figure 3–26
transaction that ensures only a single data phase is completed. In
Figure
asserted in clock cycle 6. This transaction informs the PCI MegaCore
function that the local side is ready with data but also wants to
disconnect. As a result the PCI MegaCore function disconnects after one
data phase. This figure applies to all PCI MegaCore functions, excluding
the 64-bit extension signals as noted for pci_mt32 and pci_t32.
6
3
Adr-PAR
3–26, lt_rdyn is asserted in clock cycle 5 and lt_discn is
PCI Compiler Version 10.1
4
shows an example of a disconnect during a burst read
Z
Z
Z
5
BE0_H
BE0_L
6
381
D0_H
D0_L
7
D0_H
D0_L
8
D0-H-PAR
D0-L-PAR
Adr
781
6
9
Altera Corporation
381
10
January 2011
000
11