IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 18

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

General Description
6
PCI Compiler User Guide
To ensure timing and protocol compliance, the PCI MegaCore functions
have been rigorously hardware tested. Refer to
on page 10
PCI Testbench
The PCI testbench, provided in Verilog HDL and VHDL, facilitates the
design and verification of systems that implement any of the PCI
MegaCore functions. You can build a PCI behavioral simulation
environment by using components of the PCI testbench, the IP functional
simulation model of your PCI MegaCore function variation, and the rest
of your Verilog HDL or VHDL design.
PCI Compiler with MegaWizard Plug-in Manager Flow
With this flow, you design to a low-level interface that allows custom PCI
transaction design. Because you are designing the logic to interface to the
PCI MegaCore function, you have more control of individual module
functionality.
1
For example, if you are designing a PCI-to-DDR2 SDRAM controller
interface you need to do the following:
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Specify the PCI MegaCore function parameters.
Design the ‘back end’ user design, including master control logic,
target control logic, data path first-in first-out (FIFO) buffers, and
direct memory access (DMA) engine.
Design the DDR2 SDRAM controller interface.
Specify the DDR2 SDRAM MegaCore function parameters.
Design internal PCI and DDR2 SDRAM logic blocks.
Write RTL code that connects the PCI and DDR2 SDRAM blocks.
This flow is recommended for users who have previously
designed with the PCI Compiler or whose highest priority is to
minimize design latency.
PCI Compiler Version 10.1
for more information on the hardware tests performed.
“Compliance Summary”
Altera Corporation
January 2011