IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 49

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
tmbr64
tmbr32_64
tmsr64
tmbr64_abrt
tmbr64_disc_wd
tmbr64_disc_wod
tmbr64_ret
cfg_wr_rd
tior
exp_rom_tmbr64
tmbw64
tmbw32_64
tmsw64
tmbw64_abrt
tmbw64_disc_wd
tmbw64_disc_wod
tmbw64_ret
tiow
exp_rom_tmbw64
Simulation File Name
Table 1–4. pci_mt64 & pci_t64 Target Simulation Files
Memory Burst Read, 64-Bit PCI, 64-Bit Local
Memory Burst Read, 32-Bit PCI, 64-Bit Local
Memory Single-Cycle, 64-Bit PCI, 64-Bit Local
Memory Abort, 64-Bit PCI, 64-Bit Local
Memory Disconnect with Data, 64-Bit PCI, 64-Bit Local
Memory Disconnect without Data, 64-Bit PCI, 64-Bit Local
Memory Retry, 64-Bit PCI, 64-Bit Local
Configuration Write and Read
I/O Read
Expansion ROM Memory Burst Read, 64-Bit PCI, 64-Bit Local
Memory Burst Write, 64-Bit PCI, 64-Bit Local
Memory Burst Write, 32-Bit PCI, 64-Bit Local
Memory Single-Cycle, 64-Bit PCI, 64-Bit Local
Memory Abort, 64-Bit PCI, 64-Bit Local
Memory Disconnect with Data, 64-Bit PCI, 64-Bit Local
Memory Disconnect without Data, 64-Bit PCI, 64-Bit Local
Memory Retry, 64-Bit PCI, 64-Bit Local
I/O Write
Expansion ROM Memory Burst Write, 64-Bit PCI, 64-Bit Local
Target Simulation Files
Table 1–4
<path>\pci_compiler\megawizard_flow\qexamples\
<pci_mt64 or pci_t64>\sim\target directory.
describes the Quartus II simulation files included in the
PCI Compiler Version 10.1
Target Write
Target Read
Description
PCI Compiler User Guide
Getting Started
1–15