IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 125

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
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Table 3–35. Single-Cycle Memory Read Target Transaction (Part 1 of 2)
Clock Cycle
The PCI bus is idle.
The address phase occurs.
The PCI MegaCore function latches the address and command, and decodes the address to
check if it falls within the range of one of its BARs. During clock cycle 3, the master deasserts
the
remains in the transaction. For a single-cycle memory read, this phase is the only data phase
in the transaction. The PCI MegaCore function begins to decode the address during clock
cycle 3, and if the address falls in the range of one of its BARs, the transaction is claimed.
The PCI master tri-states the
If the PCI MegaCore function detects an address hit in clock cycle 3, several events occur
during clock cycle 4:
●
●
●
●
●
The PCI MegaCore function asserts
function also drives
on the
to ensure that it is not tri-stated for a long time while waiting for valid data. Although the local
side asserts
cycle 6.
lt_rdyn
in clock cycle 6. The PCI MegaCore function registers the data into its internal pipeline on the
rising edge of clock cycle 7. The local side transfer is indicated by the
lt_dxfrn
The local side data transfer occurs if
lt_rdyn
indicate a successful data transfer.
The rising edge of clock cycle 7 registers the valid data from the
data on the
to indicate that there is valid data on the
The PCI MegaCore function informs the local-side device that it is claiming the read
transaction by asserting
the BAR range hit. In
register zero hit.
The MegaCore function drives the transaction command on
address on
The PCI MegaCore function turns on the drivers of
stopn
lt_tsr[7]
lt_tsr[8]
busy.
framen
l_adi
, getting ready to assert
is asserted in clock cycle 5, indicating that valid data is available on the
is asserted on the previous clock edge. The
Table 3–35
read target transaction. The 64-bit extension signals are not applicable to
the pci_mt32 and pci_t32 MegaCore functions.
ad
signal is low during the clock cycle where a data transfer on the local side occurs.
lt_rdyn
and
bus. The PCI MegaCore function also enables the output drivers of the
l_adro[31..0]
bus. At the same time, the PCI MegaCore function asserts the
is asserted to indicate that the pending transaction is 64-bits.
is asserted to indicate that the PCI side of the PCI MegaCore function is
req64n
lt_ackn
PCI Compiler Version 10.1
during clock cycle 5, the data transfer does not occur until clock
shows the sequence of events for a 64-bit single-cycle memory
Figure
signals and asserts
lt_framen
ad
to the local-side device to indicate that it is ready to accept data
3–7,
bus for the turn-around cycle.
.
devseln
lt_tsr[0]
devseln
lt_ackn
ad
and the bit on
Event
bus.
and
irdyn
and
is asserted on the current clock edge while
ack64n
is asserted indicating that a base address
ack64n
devseln
to indicate that only one data phase
lt_tsr[5..0]
lt_dxfrn
in clock cycle 5.
to claim the transaction. The
l_cmdo[3..0]
l_adi
,
ack64n
signal is asserted to
lt_dxfrn
Functional Description
bus and drives the
that corresponds to
,
trdyn
trdyn
l_adi
signal. The
and
, and
ad
signal
bus
bus
3–51