IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 164

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Master Mode Operation
3–90
PCI Compiler User Guide
The PCI MegaCore functions support both 64-bit and 32-bit transactions.
The pci_mt64 function supports the following 64-bit PCI memory
transactions:
■
■
1
l_hdat_ackn
lt_abortn
lt_discn
lt_rdyn
lt_framen
lt_ackn
lt_dxfrn
lt_tsr[11..0]
lirqn
cache[7..0]
cmd_reg[5..0]
stat_reg[5..0]
lm_req32n
lm_req64n
lm_lastn
lm_rdyn
lm_adr_ackn
lm_ackn
lm_dxfrn
lm_tsr[9..0]
Table 3–37. PCI MegaCore Function Signals (Part 2 of 2)
64-bit burst memory read/write
64-bit single-cycle memory read/write
Signal Name
64-bit single-cycle memory write transactions are only
supported if the Assume ack64n Response option is turned on
in the Parameterize - PCI Compiler wizard. For more
information on the Assume ack64n Response option, refer to
“Assume ack64n Response” on page
PCI Compiler Version 10.1
Master Local-side Control Signals
Target Local-side Control Signals
pci_mt64
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2–6.
Altera Corporation
pci_mt32
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January 2011