IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 139

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
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Table 3–36. Single-Cycle Memory Write Target Transactions (Part 1 of 2)
Clock
Cycle
The PCI bus is idle.
The address phase occurs.
The PCI MegaCore function latches the address and command, and decodes the address to check
if it falls within the range of one of its BARs. During clock cycle 3, the master deasserts the
and
transaction. For a single-cycle memory write target transaction, this phase is the only data phase in
the transaction. The MegaCore function uses clock cycle 3 to decode the address, and if the address
falls in the range of one of its BARs, the transaction is claimed.
If the PCI MegaCore function detects an address hit in clock cycle 3, several events occur during
clock cycle 4:
●
●
●
●
●
The PCI MegaCore function asserts
local side asserting
function in clock cycle 6.
To allow the local side ample time to issue a retry for the write cycle, the PCI MegaCore function does
not assert
asserted in clock cycle 5
The PCI MegaCore function asserts
Because
The PCI MegaCore function informs the local-side device that it is going to claim the write
transaction by asserting
BAR range hit. In
zero hit.
The PCI MegaCore function drives the transaction command on
on
The PCI MegaCore function turns on the drivers of
getting ready to assert
lt_tsr[7]
lt_tsr[8]
req64n
l_adro[31..0]
irdyn
trdyn
signals and asserts
is already asserted, this clock cycle is the first and last data phase in this cycle.
is asserted to indicate that the pending transaction is 64 bits.
is asserted to indicate that the PCI side of the PCI MegaCore function is busy.
Table 3–36
write target transaction. The 64-bit extension signals are not applicable to
the pci_mt32 and pci_t32 MegaCore functions.
in the first data phase unless the local side asserts
lt_rdyn
Figure
(Figure
.
devseln
lt_framen
3–15,
PCI Compiler Version 10.1
, indicating that it is ready to receive data from the PCI MegaCore
shows the sequence of events for a 64-bit single-cycle memory
3–15), the PCI MegaCore function delays the assertion of
irdyn
lt_tsr[0]
devseln
trdyn
and
to indicate that only one data phase remains in the
and the bit on
ack64n
to inform the PCI master that it is ready to accept data.
Event
to claim the transaction.
is asserted indicating that a base address register
in clock cycle 5.
devseln
lt_tsr[5..0]
,
ack64n
l_cmdo[3..0]
lt_rdyn
Figure 3–15
that corresponds to the
Functional Description
,
trdyn
. If
lt_rdyn
also shows the
, and
and address
stopn
framen
trdyn
is not
3–65
.