IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 63

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
Allow Variable Byte Enables During Burst Transactions
In a default master burst transaction the byte enables accompanying the
initial data word provided by the local side are used throughout the
master burst transaction. Turning on Allow Variable Byte Enables
During Burst Transactions allows byte enables to change for successive
data words during the transaction. This option affects both burst memory
read and burst memory write master transactions. However, use this
option only for burst memory write master transactions. Refer to
Memory Write Master Transaction with PCI Wait State” on page 3–117
more information. For burst memory read master transactions, you must
keep the byte enables constant throughout the transaction. Typically the
byte enable values are set to 0x00 for burst memory read master
transactions.
Use in Host Bridge Application
Turning on the Use in Host Bridge Application option allows you to
implement a host bridge design using the pci_mt64 and pci_mt32
MegaCore functions. For more information on using the pci_mt64 or
pci_mt32 MegaCore functions in a host bridge application, refer to
“Host Bridge Operation” on page
Allow Internal Arbitration Logic
Many designs that utilize the pci_mt64 or pci_mt32 MegaCore
functions as a host bridge implement other central resource functionality
in the same FPGA as the PCI interface. Turning on Allow Internal
Arbitration Logic option allows you to include the PCI bus arbiter in the
same FPGA as the PCI MegaCore function.
If the Allow Internal Arbitration Logic option is not selected, the reqn
signal output from the pci_mt64 and pci_mt32 functions is
implemented with a tri-state buffer, which prevents reqn from being
connected to internal logic and subsequently to gntn without the use of
device I/Os. Turning on Allow Internal Arbitration Logic removes the
tri-state buffer from the reqn signal output, allowing the signal to be
connected to internal FPGA logic and eliminating the need to use
additional device I/O resources or board traces.
PCI Compiler Version 10.1
3–127.
Parameter Settings
“Burst
2–5
for