IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 267

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
January 2011
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For example, if you select a page size of 512 MBytes, the maximum
number of pages is four for both hardwired and dynamically configured.
If you select a smaller page size that yields more than 16 pages and then
change to a hardwired address map, the number of pages is
automatically decreased to 16.
The Fixed Address Translation Table Contents field is disabled if you
select Dynamic Translation Table. If you select Fixed Translation Table,
the number of rows that appear in the Contents panel is the same as the
value you enter in the Number of Address Pages box. For each Avalon
Address Offset, you can set a PCI Base Address and Type value. The
choices for Type are 32-bit/64-bit memory, I/O, and configuration. Refer
to
Turning on Control Register Access Avalon Slave Port option under
Avalon CRA Port allows read/write accesses to the bridge’s registers.
Disabling this option means that no read/write accesses will be granted
to the bridge’s registers. There are two cases in which this option is
always enabled:
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“Avalon-to-PCI Address Translation” on page
16 if hardwired or 512 if dynamically configured
2 GBytes divided by the size of each page
If Dynamic Translation Table is selected in the Translation Table
panel
If PCI Host-Bridge Device is chosen as the device type on the
System Options - 1 page
PCI Compiler Version 10.1
7–35.
Parameter Settings
6–17