IPR-PCI/MT32 Altera, IPR-PCI/MT32 Datasheet - Page 114

• Manufacturer Part Number: IPR-PCI/MT32
• Description: IP CORE Renewal Of IP-PCI/MT32
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-PCI/MT32

• Software Application: IP CORE, Interface And Protocols, PCI
• Supported Families: Arria GX, Arria II GX, Cyclone, Stratix
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Function: PCI Compiler, Master/Target, 32 bit
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Configuration Registers
3–40
PCI Compiler User Guide
2..0
27..3
31..28
Table 3–25. CIS Pointer Register Format
Data Bit
adr_space_ind
adr_offset
rom_im
Mnemonic
CardBus CIS Pointer Register
The card information structure (CIS) pointer register is a 32-bit read-only
register that points to the beginning of the CIS. This optional register is
used by devices that have the PCI and CardBus interfaces on the same
silicon. By default, the PCI MegaCore functions do not enable this
register. The CIS Pointer register can be enabled and the register’s value
can be set through the wizard.
more information on the CardBus CIS pointer register, refer to the PC
Card Standard Specification, Version 2.10.
Subsystem Vendor ID Register
Subsystem vendor ID is a 16-bit read-only register that identifies add-in
cards from different vendors that have the same functionality. The value
of this register is assigned by the PCI SIG. Refer to
value of the subsystem vendor ID register is 0x0000. However, you can
change the value through the wizard.
Table 3–26. Subsystem Vendor ID Register Format
Data Bit
15..0
Read
Read
Read
Read/Write
PCI Compiler Version 10.1
sub_ven_id
Mnemonic
Address space indicator. The value of these bits indicates
that the CIS pointer register is pointing to one of the
following spaces: configuration space, memory space, or
expansion ROM space.
The PCI MegaCore functions do not support the condition
where the CIS pointer register points to the configuration
space.
Address space offset. This value gives the address
space’s offset indicated by the address space indicator.
ROM image. These bits are the uppermost bits of the
address space offset when the CIS pointer register is
pointing to an expansion ROM space.
Table 3–25
Read/Write
Read
shows this register’s format. For
Definition
PCI subsystem/vendor ID
Table
Altera Corporation
3–26. The default
Definition
January 2011